512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040
Data Sheet
SST37VF040 SST37VF020 SST37VF010 SST37VF512
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
32-pin
6
PDIP
7
8
Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SST37VF512 SST37VF010 SST37VF020 SST37VF040
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
397 ILL F02b.1
FIGURE 3: P
IN
A
SSIGNMENTS FOR
32-
PIN
PDIP
TABLE 2: P
IN
D
ESCRIPTION
Symbol
A
MS1
-A
0
DQ
7
-DQ
0
CE#
WE#
OE#
V
DD
V
SS
NC
Pin Name
Address Inputs
Data Input/output
Chip Enable
Write Enable
Output Enable
Power Supply
Ground
No Connection
Unconnected pins.
T2.1 397
Functions
To provide memory addresses.
To output data during Read cycles and receive input data during Program cycles.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To program or erase (WE# = V
IL
pulse during Program or Erase)
To gate the data output buffers during Read operation when low
To provide 3.0V supply (2.7-3.6V)
1. A
MS
= Most significant address
A
MS
= A
15
for SST37VF512, A
16
for SST37VF010, A
17
for SST37VF020, and A
18
for SST37VF040
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
397
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
