512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TABLE 5: DC O
PERATING
C
HARACTERISTICS
V
DD
= 3.0-3.6V
FOR
SST39LF512/010/020/040
AND
2.7-3.6V
FOR
SST39VF512/010/020/040
1
Limits
Symbol
I
DD
Parameter
Power Supply Current
Read
2
Program and Erase
3
I
SB
I
LI
I
LO
V
IL
V
IH
V
IHC
V
OL
V
OH
Standby V
DD
Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
V
DD
-0.2
0.7V
DD
V
DD
-0.3
0.2
20
30
15
1
10
0.8
mA
mA
µA
µA
µA
V
V
V
V
V
Min
Max
Units
Test Conditions
Address input=V
ILT
/V
IHT
, at f=1/T
RC
Min
V
DD
=V
DD
Max
CE#=V
IL
, OE#=WE#=V
IH
, all I/Os open
CE#=WE#=V
IL
, OE#=V
IH
CE#=V
IHC
, V
DD
=V
DD
Max
V
IN
=GND to V
DD
, V
DD
=V
DD
Max
V
OUT
=GND to V
DD
, V
DD
=V
DD
Max
V
DD
=V
DD
Min
V
DD
=V
DD
Max
V
DD
=V
DD
Max
I
OL
=100 µA, V
DD
=V
DD
Min
I
OH
=-100 µA, V
DD
=V
DD
Min
T5.7 1150
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C
(room temperature), and V
DD
= 3V for VF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the
Multi-Purpose Flash Power Rating
application note for further information.
3. 30 mA max for Erase operations in the industrial temperature range.
TABLE 6: R
ECOMMENDED
S
YSTEM
P
OWER
-
UP
T
IMINGS
Symbol
T
PU-READ1
T
PU-WRITE1
Parameter
Power-up to Read Operation
Power-up to Program/Erase Operation
Minimum
100
100
Units
µs
µs
T6.1 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: C
APACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
C
I/O1
C
IN1
Description
I/O Pin Capacitance
Input Capacitance
Test Condition
V
I/O
= 0V
V
IN
= 0V
Maximum
12 pF
6 pF
T7.0 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: R
ELIABILITY
C
HARACTERISTICS
Symbol
N
END1,2
T
DR1
I
LTH1
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
10,000
100
100 + I
DD
Units
Cycles
Years
mA
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
T8.3 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. N
END
endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2005 Silicon Storage Technology, Inc.
S71150-09-000
1/06
8
SST [ SILICON STORAGE TECHNOLOGY, INC ]
