512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TOP VIEW (balls facing down)
6
A2
A8
A17
A14
A9
A13
A11
NC1
OE#
A10
CE#
5
A1
DQ7 DQ5 DQ6
DQ3 DQ4
1150 34-wfbga MM P5.0
4
A0
V
DD
WE#
A16
A12
A18
A15
A6
A7
A5
A4
NC2
A3
A0
A2
3
CE#
DQ2
V
SS
2
V
SS
DQ0 DQ1
A1
1
A
B
C
D
E
F
G
H
J
Note: For SST39LF020, ball B3 is "No Connect"
For SST39LF010, balls B3 and A5 are "No Connect"
FIGURE 4: P
IN
A
SSIGNMENT FOR
34-
BALL
WFBGA (4
MM X
6
MM
)
FOR
1 M
BIT AND
2 M
BIT
TABLE 2: P
IN
D
ESCRIPTION
Symbol
A
MS1
-A
0
DQ
7
-DQ
0
Pin Name
Address Inputs
Data Input/output
Functions
To provide memory addresses. During Sector-Erase A
MS
-A
12
address lines will select the
sector. During Block-Erase A
MS
-A
16
address lines will select the block.
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/020/040
CE#
OE#
WE#
V
DD
V
SS
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Unconnected pins.
T2.1 1150
1. A
MS
= Most significant address
A
MS
= A
15
for SST39LF/VF512, A
16
for SST39LF/VF010, A
17
for SST39LF/VF020, and A
18
for SST39LF/VF040
TABLE 3: O
PERATION
M
ODES
S
ELECTION
Mode
Read
Program
Erase
Standby
Write Inhibit
Product Identification
Software Mode
V
IL
V
IL
V
IH
See Table 4
T3.4 1150
CE#
V
IL
V
IL
V
IL
V
IH
X
X
OE#
V
IL
V
IH
V
IH
X
V
IL
X
WE#
V
IH
V
IL
V
IL
X
X
V
IH
DQ
D
OUT
D
IN
X
1
High Z
High Z/ D
OUT
High Z/ D
OUT
Address
A
IN
A
IN
Sector address,
XXH for Chip-Erase
X
X
X
1. X can be V
IL
or V
IH
, but no other value.
©2005 Silicon Storage Technology, Inc.
S71150-09-000
1/06
6
SST [ SILICON STORAGE TECHNOLOGY, INC ]
