1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
10
SW0
SW5
1147 F17.1
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 10)
SA = Sector Address
X
A
A
= Most significant address
MS
MS
= A for SST39SF010A, A for SST39SF020A, and A for SST39SF040
16 17 18
FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-byte Sequence for
Software ID Entry
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
IDA
T
WP
AA
T
WPH
55
SW1
T
AA
DQ
7-0
90
BF
Device ID
SW0
SW2
1147 F09.2
Device ID = B5H for SST39SF010A, B6H for SST39SF020A, and B7H for SST39SF040
FIGURE 11: SOFTWARE ID ENTRY AND READ
©2003 Silicon Storage Technology, Inc.
S71147-06-000
8/04
13
SST [ SILICON STORAGE TECHNOLOGY, INC ]
