1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
Read
The Read operation of the SST39LF/VF100 is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device selec-
tion. When CE# is high, the chip is deselected and only
standby power is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
Chip-Erase Operation
The SST39LF/VF100 provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 7 for timing diagram,
and Figure 16 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Word-Program Operation
The SST39LF/VF100 are programmed on a word-by-word
basis. Before programming, one must ensure that the sec-
tor in which the word is programmed is erased. The Pro-
gram operation consists of three steps. The first step is the
three-byte load sequence for Software Data Protection.
The second step is to load word address and word data.
During the Word-Program operation, the addresses are
latched on the falling edge of either CE# or WE#, which-
ever occurs last. The data is latched on the rising edge of
either CE# or WE#, whichever occurs first. The third step is
the internal Program operation which is initiated after the
rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be com-
pleted within 20 µs. See Figures 3 and 4 for WE# and CE#
controlled Program operation timing diagrams and Figure
valid reads are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform addi-
tional tasks. Any commands issued during the internal Pro-
gram operation are ignored.
Write Operation Status Detection
The SST39LF/VF100 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal program or erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6
. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 2 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The address lines
A
11
-A
15
are used to determine the sector address. The
sector address is latched on the falling edge of the sixth
WE# pulse, while the command (30H) is latched on the ris-
ing edge of the sixth WE# pulse. The internal Erase opera-
tion begins after the sixth WE# pulse. The End-of-Erase
operation can be determined using either Data# Polling or
Toggle Bit methods. See Figure 8 for timing waveforms.
Any commands issued during the Sector-Erase operation
are ignored.
Data# Polling (DQ
7
)
When the SST39LF/VF100 are in the internal Program
operation, any attempt to read DQ
7
will produce the com-
plement of the true data. Once the Program operation is
completed, DQ
7
will produce true data. The device is then
ready for the next operation. During internal Erase opera-
tion, any attempt to read DQ
7
will produce a ‘0’. Once the
internal Erase operation is completed, DQ
7
will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector- or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 5 for Data# Polling
timing diagram and Figure 14 for a flowchart.
©2001 Silicon Storage Technology, Inc.
S71129-02-000 6/01
363
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