16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
TRC
ADDRESS AMS-0
TAA
CE#
TCE
OE#
VIH
WE#
TOLZ
TOE
TOHZ
TCHZ
HIGH-Z
DATA VALID
1243 F02.0
DQ15-0
HIGH-Z
TCLZ
TOH
DATA VALID
Note:
A
MS
= Most Significant Address
A
MS
= A
20
for SST39VF168x
FIGURE 3: R
EAD
C
YCLE
T
IMING
D
IAGRAM
INTERNAL PROGRAM OPERATION STARTS
TBP
ADDRESS AMS-0
AAA
TAH
TWP
WE#
TAS
OE#
TCH
CE#
TCS
DQ7-0
AA
SW0
55
SW1
A0
SW2
DATA
BYTE
(ADDR/DATA)
1243 F03.0
555
AAA
ADDR
TDH
TWPH
TDS
Note:
A
MS
= Most Significant Address
A
MS
= A
20
for SST39VF168x
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.
FIGURE 4: WE# C
ONTROLLED
P
ROGRAM
C
YCLE
T
IMING
D
IAGRAM
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
13
SST [ SILICON STORAGE TECHNOLOGY, INC ]
