8 Mbit LPC Flash
SST49LF080A
Data Sheet
TABLE 5: LPC READ CYCLE
Clock
Cycle
Field
Name
LAD[3:0]
Direction
Field Contents
LAD[3:0]1
Comments
1
START
0000
IN
LFRAME# must be active (low) for the part to respond. Only the
last start field (before LFRAME# transitions high) should be rec-
ognized.
2
CYCTYPE
+ DIR
010X
IN
IN
Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle.
Bit 1 indicates the type of transfer “0” for Read. Bit 0 is reserved.
3-10
ADDRESS
YYYY
Address Phase for Memory Cycle. LPC protocol supports a 32-
bit address phase. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble fist. See Table
3 for address bits definition and Table 4 for valid memory
address range.
11
12
13
TAR0
TAR1
SYNC
1111
1111 (float)
0000
IN
In this clock cycle, the host has driven the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
then Float
Float
then OUT
The SST49LF080A takes control of the bus during this cycle
OUT
The SST49LF080A outputs the value 0000b indicating that data
will be available during the next clock cycle.
14
15
16
DATA
DATA
TAR0
ZZZZ
ZZZZ
1111
OUT
OUT
This field is the least-significant nibble of the data byte.
This field is the most-significant nibble of the data byte.
IN
In this clock cycle, the host has driven the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
then Float
17
TAR1
1111 (float)
Float
The SST49LF080A takes control of the bus during this cycle
then OUT
T5.0 1235
1. Field contents are valid on the rising edge of the present clock cycle.
CE#
LCLK
LFRAME#
CYCTYPE
+
Start
Address
TAR0
1111b Tri-State 0000b
2 Clocks
TAR1
Sync
Data
DIR
0000b 010Xb
1 Clock 1 Clock
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
Load Address in 8 Clocks
A[7:4]
A[3:0]
D[3:0]
D[7:4]
TAR
LAD[3:0]
1 Clock Data Out 2 Clocks
1235 F04.0
FIGURE 4: LPC READ CYCLE WAVEFORM
©2003 Silicon Storage Technology, Inc.
S71235-00-000
4/03
12
SST [ SILICON STORAGE TECHNOLOGY, INC ]
