FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
TABLE 14-7: DC Electrical Characteristics for SST89V516RDx
T
A
= -40°C to +85°C; V
DD
= 2.7-3.6V; V
SS
= 0V
Symbol
V
IL
V
IH
V
IH1
V
OL
V
OL
Parameter
Input Low Voltage
Input High Voltage
Input High Voltage (XTAL1, RST)
Output Low Voltage (Ports 1.5, 1.6, 1.7)
Output Low Voltage (Ports 1, 2,
3)
1
Test Conditions
2.7 < V
DD
< 3.6
2.7 < V
DD
< 3.6
2.7 < V
DD
< 3.6
V
DD
= 2.7V
I
OL
= 16mA
V
DD
= 2.7V
I
OL
= 100µA
2
I
OL
= 1.6mA
2
I
OL
= 3.5mA
2
V
OL1
Output Low Voltage (Port 0, ALE, PSEN#)
1,3
V
DD
= 2.7V
I
OL
= 200µA
2
I
OL
= 3.2mA
2
V
OH
Output High Voltage (Ports 1, 2, 3, ALE,
PSEN#)
4
V
DD
= 2.7V
I
OH
= -10µA
I
OH
= -30µA
I
OH
= -60µA
V
OH1
Output High Voltage (Port 0 in External Bus Mode)
4
V
DD
= 2.7V
I
OH
= -200µA
I
OH
= -3.2mA
V
BOD
I
IL
I
TL
I
LI
R
RST
C
IO
I
DD
Brown-out Detection Voltage
Logical 0 Input Current (Ports 1, 2, 3)
Logical 1-to-0 Transition Current (Ports 1, 2, 3)
5
Input Leakage Current (Port 0)
RST Pull-down Resistor
Pin Capacitance
6
Power Supply Current
IAP Mode
@ 33 MHz
Active Mode
@ 33 MHz
Idle Mode
@ 33 MHz
Power-down Mode (min. V
DD
= 2V)
T
A
= 0°C to +70°C
T
A
= -40°C to +85°C
21
45
55
mA
µA
µA
T14-7.1 1273
Min
-0.5
0.2V
DD
+ 0.9
0.7V
DD
Max
0.7
V
DD
+ 0.5
V
DD
+ 0.5
1.0
0.3
0.45
1.0
0.3
0.45
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
- 0.3
V
DD
- 0.7
V
DD
- 1.5
V
DD
- 0.3
V
DD
- 0.7
2.35
2.55
-75
-650
±10
225
15
V
µA
µA
µA
KΩ
pF
V
IN
= 0.4V
V
IN
= 2V
0.45 < V
IN
< V
DD
-0.3
@ 1 MHz, 25°C
47
30
mA
mA
1. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
15mA
Maximum I
OL
per 8-bit port:
26mA
Maximum I
OL
total for all outputs: 71mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and Ports 1 & 3. The noise
due to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In
the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
67
SST [ SILICON STORAGE TECHNOLOGY, INC ]
