FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Data Sheet
TABLE
Operation
Read-ID
Chip-Erase
Block-Erase
Sector-Erase
Byte-Program
Byte-Verify (Read)
Prog-SC0
Prog-SC1
Prog-SB1
Prog-SB2
Prog-SB3
Enable-Clock-Double
4-2: E
XTERNAL
H
OST
M
ODE
C
OMMANDS
RST
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
V
IH1
PSEN#
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
PROG#/
ALE
V
IH
⇓
1
⇓
⇓
⇓
V
IH
⇓
⇓
⇓
⇓
⇓
⇓
FOR
SST89E/V554RC
P3[7]
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IH
P3[6]
V
IL
V
IL
V
IH
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
P2[7]
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
P2[6]
V
IL
V
IH
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
P0[7:0]
DO
X
X
X
DI
DO
X
X
X
X
X
X
P3[5:4]
P2[5:0]
AH
X
A[15:13]
EA#
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
P1[7:0]
AL
X
X
AL
AL
AL
X
X
X
X
X
X
T4-2.0 1207
AH
AH
AH
5AH
AAH
X
X
X
55H
1. Symbol
⇓
signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input.
All other combinations of the above input pins are invalid and may result in unexpected behaviors.
Note:
V
IL
= Input Low Voltage;
V
IH
= Input High Voltage;
V
IH1
= Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;
AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:13] = 0xxb for Block 0 and A[15:13] = 111b for Block 1
V
SS
V
DD
RST
0
Port 0
6
7
0
Input/
Output
Data
Bus
0
1
2
1
2
Port 2
Port 3
3
4
5
6
Address Bus
A
13
-A
8
Ready/Busy#
Address Bus
A
15
-A
14
A
14
A15
3
4
5
6
7
7
0
Flash
Control Signals
Address Bus
A
7
-A
0
Flash
Control Signals
Port 1
6
7
EA# ALE / PSEN#
PROG#
1207 F04.3
FIGURE
4-1: I/O P
IN
A
SSIGNMENTS
FOR
E
XTERNAL
H
OST
M
ODE
©2003 Silicon Storage Technology, Inc.
S71207-04-000
12/03
33
SST [ SILICON STORAGE TECHNOLOGY, INC ]
