FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Data Sheet
The table below summarizes various clock inputs at two common frequencies.
TABLE
8-2: PCA T
IMER
/C
OUNTER
I
NPUTS
Clock Increments
PCA Timer/Counter Mode
Mode 0: f
OSC
/12
Mode 1:
Mode 2: Timer 0 Overflows
1
Timer 0 programmed in:
8-bit mode
16-bit mode
8-bit auto-reload
Mode 3: External Input MAX
256 µsec
65 msec
1 to 255 µsec
0.66 µsec
192 µsec
49 µsec
0.75 to 191 µsec
0.50 µsec
T8-2.0 1207
12 MHz
1 µsec
330 nsec
16 MHz
0.75 µsec
250 nsec
1. In Mode 2, the overflow interrupt for Timer 0 does not need to be enabled.
CMOD’s four possible timer modes with and without the overflow interrupt enabled are shown below. This list
assumes that PCA will be left running during idle mode.
TABLE
8-3: CMOD V
ALUES
CMOD Value
PCA Count Pulse Selected
Internal clock, f
OSC
/12
Internal clock, f
OSC
/4
Timer 0 overflow
External clock at P1.2
Without Interrupt Enabled
00H
02H
04H
06H
With Interrupt Enabled
01H
03H
05H
07H
T8-3.0 1207
The CCON register is associated with all PCA timer functions. It contains run control bits and flags for the PCA
timer (CF) and all modules. To run the PCA the CR bit (CCON.6) must be set by software. Clearing the bit, will turn
off PCA. When the PCA counter overflows, the CF (CCON.7) will be set, and an interrupt will be generated if the
ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Each module has its own timer
interrupt or capture interrupt flag (CCF0 for module 0, CCF4 for module 4, etc.). They are set when either a match
or capture occurs. These flags can only be cleared by software. (See “PCA Timer/Counter Control Register
(CCON)” on page 25.)
©2003 Silicon Storage Technology, Inc.
S71207-04-000
12/03
49
SST [ SILICON STORAGE TECHNOLOGY, INC ]
