ST24/25C04, ST24/25W04
ory address bits (A7-A3) are the same inside one
block. The master sends from one up to 8 bytes of
data, which are each acknowledged by the mem-
ory. After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t
W
) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master.
Figure 8. Write Cycle Polling using ACK
WRITE Cycle
in Progress
Figure 7. Memory Protection
Protect Location
8 byte
boundary
address
b7
1FFh
Protect Flag
Enable = 0
Disable = 1
b3 b2
X
X
Block 1
100h
Block 0
AI00855B
START Condition
DEVICE SELECT
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by ST24xxx
ACK
Returned
YES
NO
Next
Operation is
Addressing the
Memory
YES
ReSTART
Send
Byte Address
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01099B
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