M24128-BW, M24128-BR, M24256-BW, M24256-BR
SUMMARY DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32K x 8 bits (M24256-BW and M24256-
BR) and 16K x 8 bits (M24128-BW and M24128-
BR).
Figure 2. Logic Diagram
VCC
3
E0-E2
SCL
WC
M24256-B
M24128-B
SDA
VSS
AI02809
限
SCL
WC
V
CC
V
SS
Serial Clock
公
SDA
Serial Data
司
E0, E1, E2
Chip Enable
，
Table 2. Signal Names
18
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in
terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset
In order to prevent inadvertent Write operations
during Power Up, a Power On Reset (POR) circuit
is implemented.
At Power Up, the device will not respond to any in-
struction until V
CC
has reached the POR threshold
voltage (this threshold is lower than the V
CC
mini-
mum operating voltage defined in
and
In the same way, as soon as V
CC
drops
from the normal operating voltage, below the POR
threshold voltage, all the operations are disabled
and the device will not respond to any instruction.
Prior to selecting and issuing instructions to the
memory, a valid and stable V
CC
voltage must be
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
the internal write cycle (t
W
).
Figure 3. DIP, SO and TSSOP Connections
66
43
Write Control
科
技
有
41
58
5，
QQ
M24256-B
M24128-B
Supply Voltage
Ground
讯
E0
E1
E2
VSS
深
I
2
C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
2
C bus definition.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
1
2
3
4
：
合
AI02810B
圳
市
金
Note: See
section for package dimen-
sions, and how to identify pin-1.
4/25
71
44
51
8
8
7
6
5
VCC
WC
SCL
SDA
19
STMICROELECTRONICS [ STMICROELECTRONICS ]
