Ordering information
STM8S105xx
[ ] 1: Port D0 alternate function = TIM1_BKIN.
AFR4
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
[ ] 1: Port D7 alternate function = TIM1_CH4.
AFR5
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
[ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate
function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N,
port B0 alternate function = TIM1_CH1N.
AFR6
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description
(check only one option)
[ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate
function = I2C_SCL.
AFR7
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
(check only one option)
[ ] 1: Port D4 alternate function = BEEP.
OPT3 watchdog
WWDG_HALT
[ ] 0: No reset generated on halt if WWDG active.
[ ] 1: Reset generated on halt if WWDG active.
(check only one option)
WWDG_HW
[ ] 0: WWDG activated by software.
[ ] 1: WWDG activated by hardware.
(check only one option)
IWDG_HW
[ ] 0: IWDG activated by software.
[ ] 1: IWDG activated by hardware.
(check only one option)
LSI_EN
[ ] 0: LSI clock is not available as CPU clock source.
[ ] 1: LSI clock is available as CPU clock source.
(check only one option)
HSITRIM
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR
register.
(check only one option)
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR
register.
OPT4 wakeup
PRSC
[ ] for 16 MHz to 128 kHz prescaler.
[ ] for 8 MHz to 128 kHz prescaler.
[ ] for 4 MHz to 128 kHz prescaler.
(check only one option)
120/127
DocID14771 Rev 9