STM8S105xx
Option bytes
Addr.
Option
name
Option Option bits
byte no.
7
6
5
4
3
2
1
0
Factory
default
setting
0x480C
0x480D
0x480E
0x487E
0x487F
Bootloader
Reserved
NOPT6
OPT7
NOPT7
OPTBL
NOPTBL
Reserved
Reserved
Reserved
BL[7:0]
NBL[7:0]
FFh
00h
FFh
00h
FFh
Table 13: Option byte description
Option byte no.
OPT0
Description
ROP[7:0]
Memory readout protection (ROP)
AAh: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
OPT1
UBC[7:0]
User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03: Page 0 to 4 defined as UBC, memory write-protected
...
0x3E: Pages 0 to 63 defined as UBC, memory write-protected
Other values: Reserved
Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.
OPT2
AFR[7:0]
Refer to following table for the alternate function remapping
decriptions of bits [7:2].
OPT3
HSITRIM:High
speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
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