UPSD3233 参数 Datasheet PDF下载

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

Table 103. Power Management Mode Registers PMMR2

Bit 0

Bit 1

Bit 2

X

X

PLD Array

WR

PLD Array

RD

PLD Array

PSEN

PLD Array

ALE

X

X

0

0

Not used, and should be set to zero.

Not used, and should be set to zero.

0 = on WR input to the PLD AND Array is connected.

1 = off WR input to PLD AND Array is disconnected, saving power.

0 = on RD input to the PLD AND Array is connected.

1 = off RD input to PLD AND Array is disconnected, saving power.

0 = on PSEN input to the PLD AND Array is connected.

1 = off PSEN input to PLD AND Array is disconnected, saving power.

0 = on ALE input to the PLD AND Array is connected.

1 = off ALE input to PLD AND Array is disconnected, saving power.

0

0

Not used, and should be set to zero.

Not used, and should be set to zero.

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers.

Table 104. APD Counter Operation

APD Enable Bit

0

1

1

ALE Level

X

Pulsing

0 or 1

Not Counting

Not Counting

Counting (Generates PDN after 15 Clocks)

APD Counter

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