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UPSD3233 参数 Datasheet PDF下载

UPSD3233图片预览
型号: UPSD3233
PDF下载: 下载PDF文件 查看货源
内容描述: 闪存可编程系统设备与8032微控制器内核 [Flash Programmable System Devices with 8032 Microcontroller Core]
分类和应用: 闪存微控制器
文件页数/大小: 170 页 / 2708 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Signal
Name
PWM1
PWM2
PWM3
PWM4
USB–
V
REF
RD_
WR_
PSEN_
ALE
RESET_
XTAL1
XTAL2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Function
Pin No.
In/Out
Basic
25
23
19
18
8
70
65
62
63
4
68
48
49
35
34
32
28
26
24
22
21
80
78
76
74
73
72
67
66
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
Pull-up resistor required (2kΩ for 3V
devices, 7.5kΩ for 5V devices)
Reference Voltage input for ADC
READ signal, external bus
WRITE signal, external bus
PSEN signal, external bus
Address Latch signal, external bus
Active low RESET input
Oscillator input pin for system clock
Oscillator output pin for system clock
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
General I/O port pin
1.
2.
3.
PLD Macro-cell outputs
PLD inputs
Latched Address Out (A0-
A7)
1.
2.
3.
4.
PLD Macro-cell outputs
PLD inputs
Latched Address Out (A0-
A7)
Peripheral I/O Mode
Alternate
8-bit Pulse Width Modulation
output 1
8-bit Pulse Width Modulation
output 2
8-bit Pulse Width Modulation
output 3
Programmable 8-bit Pulse Width
modulation output 4
Port Pin
P4.4
P4.5
P4.6
P4.7
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