uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Table 145. ISC Timing (3V Devices)
Symbol
t
ISCCF
t
ISCCH
t
ISCCL
t
ISCCFP
t
ISCCHP
t
ISCCLP
t
ISCPSU
t
ISCPH
t
ISCPCO
t
ISCPZV
t
ISCPVZ
Parameter
Clock (TCK, PC1) Frequency (except for PLD)
Clock (TCK, PC1) High Time (except for PLD)
Clock (TCK, PC1) Low Time (except for PLD)
Clock (TCK, PC1) Frequency (PLD only)
Clock (TCK, PC1) High Time (PLD only)
Clock (TCK, PC1) Low Time (PLD only)
ISC Port Set Up Time
ISC Port Hold Up Time
ISC Port Clock to Output
ISC Port High-Impedance to Valid Output
ISC Port Valid Output to High-Impedance
Conditions
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
240
240
12
5
30
30
30
40
40
2
Min
Max
12
Unit
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.
2. For Program or Erase PLD only.
Figure 87. MCU Module AC Measurement I/O Waveform
VCC – 0.5V
0.2 VCC + 0.9V
Test Points
0.2 VCC – 0.1V
AI06650
0.45V
Note: AC inputs during testing are driven at V
CC
–0.5V for a logic '1,' and 0.45V for a logic '0.'
Timing measurements are made at V
IH
(min) for a logic '1,' and V
IL
(max) for a logic '0'
Figure 88. PSD Module AC Float I/O Waveform
VOH – 0.1V
Test Reference Points
VLOAD – 0.1V
0.2 VCC – 0.1V
VOL + 0.1V
AI06651
VLOAD + 0.1V
Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to
float when a 100mV change from the loaded V
OH
or V
OL
level occurs
I
OL
and I
OH
≥
20mA
162/170
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