SMH4042A
V
CC
&
HST_3V_MON
V
TRIP
V
RVALID
LOCAL_PCI_RST#
RESET
BD_SEL1# &
BD_SEL2#
t
HSE
VGATE3 &
VGATE5
t
SLEW
V
OHVG
DRVREN#
CARD_3V_MON &
CARD_5V_MON
V
TRIP
t
PURST
HEALTHY#
SGNL_VLD#
2070 Fig01
Figure 1. Card Insertion Timing Diagram
Symbol
t
VTPD
t
VTR
t
PRLPR
V
RVALID
t
SLEW
t
HSE
t
PURST
t
GLITCH
t
OCF
t
OCVG
t
CBTC
Description
V
TRIP
to Power Down Delay, Host V ltage Input
o
V
TRIP
to Reset Output Delay, Card V ltage Input
o
PCI_RST# to LOCAL_PCI_RST#
Local Reset Output V lid
a
Slew Rate
BD_SEL# to Power On Delay, BD_SEL Noise Filter
Reset Timeout
Glitch Reject Pulse Width
Over-Current to Fault#
Over-Current to VGA E Off
T
Circuit Breaker Time Constant, Power up
Circuit Breaker Time Constant, Operating
Table 1. Card Insertion Timing
Min.
Typ.
1
1
0.1
Max.
5
5
1
Units
µs
µs
µs
V
1
250
100
100
150
150
200
200
40
1
1
4
16
V/s
ms
ms
ns
µs
µs
µs
µs
2037 Table01 2.0
SUMMIT MICROELECTRONICS, Inc.
2070
9.1 5/27/03
7
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
