SMH4803
ENPGA (16)
The ENPGA input controls the PG2# and PG3# outputs.
When ENPGA is pulled low, the PG2# output is immedi-
ately placed in a high impedance state. If ENPGA is driven
high, then the PG2# output will immediately be driven low,
provided PG1# has been active for at least t
PGD
.
PG3# (17)
PG3# is an open drain active low output with no internal
pull-up. PG3# is the last power good signal to be enabled
after Vgate, PG1# and PG2# have been turned on. PG3#
is delayed PG
D
after PG2# is active and 2xPG
D
after
PG1# is active. PG3# can be used to switch a third load
or a DC/DC converter.
PG1# (18)
PG1# is an open drain active low output with no internal
pull-up. PG1# is enabled after Vgate is enabled and
voltage across the load is within spec. PG1# can be used
to switch a load or enable a DC/DC converter.
PG2# (19)
PG2# is an open drain active low output with no internal
pull-up. PG2# is enabled after Vgate and PG1# have been
turned on. PG2# is delayed PG
D
after PG1# is active.
PG2# can be used to switch a second load or a DC/DC
converter.
V
DD
(20)
V
DD
is the positive supply connection. An internal shunt
regulator connected between V
DD
and V
SS
develops
approximately 12 volts that supplies the SMH4803. A
resistor must be placed in series with the V
DD
pin to limit
the regulator current (RD in the application illustrations).
PROGRAMMABLE FEATURES
Because the SMH4803 is electrically programmable it
can be fine-tuned for a wide variety of applications prior to
shipment to the customer. Because of this a manufacturer
can use a common part type across a wide range of
boards that are used on a common host but have different
electrical loads, power-on timing requirements, host volt-
age monitoring needs etc.
This ability to use a common solution across many plat-
forms shifts the focus of design away from designing a
new power interface for each board to concentrating on
the value added back-end logic.
Because the programming of the features is done at final
test all combinations (all 128 possibilities) are readily
available as off the shelf stock items.
Power Good Delay
The PG delay timer that controls the delay from PG1# to
PG2# and PG2# to PG3# being asserted can be set to
typical values of 5ms, 20ms, 80ms or 160ms.
Quick-Trip Circuit Breaker Threshold
The Quick-Trip circuit breaker threshold can be set to
200mV, 100mV, 60mv or OFF. This is the threshold
voltage drop across R
S
that is placed between V
SS
and
CBSense.
Circuit Breaker Delay
The circuit breaker delay defines the period of time the
voltage drop across R
S
is greater than 50mV but less than
V
QCB
before the Vgate output will be shut down. This is
effectively a filter to prevent spurious shutdowns of Vgate.
The delays that can be programmed are 5µs, 50µs, 150µs
and 400µs.
Pin Detect
The Pin Detect function can be enabled or disabled.
SUMMIT MICROELECTRONICS
2041 8.4 6/15/00
9
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
