SMH4814
Preliminary Information
I
2
C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100/400kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to V
SS
. See Figure 4
Timing Diagram.
100kHz
400kHz
Symbol Description
Conditions
Min Typ
Max
Min Typ
Max Units
f
SCL
t
LOW
t
HIGH
t
BUF
t
SU:STA
t
HD:STA
t
SU:STO
t
AA
t
DH
t
R
t
F
t
SU:DAT
t
HD:DAT
TI
t
WR
SCL Clock Frequency
Clock Low Period
Clock High Period
Bus Free Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Clock Edge to Data Valid
Data Output Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Filter SCL and SDA
Write Cycle Time
Noise suppression
Memory Array
SCL low to valid
SDA (cycle n)
SCL low (cycle n+1)
to SDA change
Note
1/
Note
1/
Before New Transmission
-
Note
1/
0
4.7
4.0
4.7
4.7
4.0
4.7
0.2
0.2
100
0
1.3
0.6
1.3
0.6
0.6
0.6
400
KHz
µs
µs
µs
µs
µs
µs
3.5
0.2
0.2
0.9
µs
µs
1000
300
250
0
100
5
150
0
100
1000
300
ns
ns
ns
ns
ns
5
ms
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
t
R
SCL
t
SU:SDA
SDA
(IN)
t
F
t
HD:SDA
t
HIGH
t
W R (For W rite Operation O nly)
t
LOW
t
SU:DAT
t
SU:STO
t
BUF
t
HD:DAT
t
AA
SDA
(OUT)
t
DH
Figure 4 . Basic I
2
C serial interface timing diagram for the Bus Interface and Memory timing. The table above
lists the AC timing parameters. One bit of data is transferred during each clock pulse. Note that data must
remain stable when the clock is high.
Summit Microelectronics, Inc
2080 2.0 07/21/05
10
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
