SMM153
INTERNAL BLOCK DIAGRAM
VREF
FAULT#
VDD
VDD_CAP
GND
COMP1
VREF
VREF = 1.25V
OV/UV
0.5V/1.25V
Output
Control
Glitch
Filter
OV/UV
COMP2
50kΩ
A0
A1
A2
SCL
SDA
WP
I
2
C
Interface
Clock
10-Bit
ADC
MUX
CAPM+
CAPM-
GPIO0
GPIO1
GPIO2
GPIO3
Control
Logic
EE
Configuration
Registers
& Memory
25kΩ
25kΩ
VM+
VM -
CAPC
CS+
250kΩ
DIFF
AMP
CS-
Figure 2 – SMM153 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
SDA
GPIO3
VREF
N/C
N/C
VDD_CAP
GPIO2
28 27 26 25 24 23 22
1
2
3
4
5
6
7
8
9 10 11 12 13 14
21
20
19
28-Pad 5x5 QFN
Top View
Pin 1
SCL
A2
GPIO0
A1
GND
A0
GND
SMM150
18
17
16
15
VDD
N/C
COMP1
CS+
CS-
CAPC
VM-
Summit Microelectronics, Inc
WP
GPIO1
CAPM+
FAULT#
COMP2
CAPM-
VM+
2134 3.0 1/20/2010
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