SMM766
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min
Typ
Max
V
IH
Input high voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#)
3
Input low voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#)
3
Open drain outputs (RST#,
FS#, PWR_ON, HEALTHY,
FAULT#, PUPx, SEQ_LINK)
Output low current
Positive sense voltage
Monitor threshold step size
Internal temperature sensor
accuracy
Temperature threshold step
size
Internal 1.25V
REF
output
voltage
Internal V
REF
temperature
coefficient
Internal V
REF
accuracy
External V
REF
voltage range
External V
REF
=1.25V, ±0.1%,
total PUPx I
SINK
< 3ma, V
SENSE
<
3.5V
External V
REF
=1.25V, ±0.1%,
total PUPx I
SINK
< 3ma, V
SENSE
>
3.5V
Internal V
REF
=1.25V, total
PUPx I
SINK
< 3ma
VDD_CAP voltage at which
the PUP, RST#, HEALTHY
and FAULT#, FS#, PWR_ON
SEQ_LINK, outputs are valid
VDD_CAP rising
VDD_CAP falling
Internally regulated to 3.6V
Internally regulated to 5.5V
Internally regulated to 3.6V
Internally regulated to 5.5V
0.8 x
VDD_CAP
0.7 x
VDD_CAP
0.2 x
VDD_CAP
0.3 x
VDD_CAP
Unit
V
V
V
V
V
mA
V
mV
o
o
o
V
IL
V
OL
I
OL
V
SENSE
V
MONITOR
t
SA
t
MONITOR
V
REF
V
REF
TC
V
REF
ACC
Ext V
REF
I
SINK
= 1mA
Note – Total I
SINK
from all PUPx pins
should not exceed 6mA or ADOC
ACC
specification will be affected
0
0
+0.3
5
-3
-5
0.25
1.24
1.25
0.4
1.0
VDD_CAP
VM pin
VM, AIN1/AIN2 pins
Commercial temp range
Industrial temp range
Internal temp sensor
+3
+5
C
C
C
1.26
+0.25
+0.15
+0.4
VDD_CAP
V
%
%
%
V
%
–40
°
C to +85
°
C
–5
°
C to +70
°
C
-0.25
-0.15
-0.4
0.5
-0.2
0.1
+0.2
ADOC
ACC
ADOC (Active DC Output
Control)/margin accuracy
-0.5
-0.5
0.3
0.3
1
2.6
2.5
+0.5
+0.5
%
%
V
V
V
V
OUT_VALID
Minimum output valid voltage
UVLO (Under Voltage Lockout)
threshold
4
UVLO
Note 1 – Range depends on internal regulator set to 3.6V or 5.5V see 12VIN specification.
Note 2 – See Application Note 37 which describes the type of capacitors to use to obtain minimum leakage.
Note 3 – All logic levels are derived with respect to the voltage present on VDD_CAP, when supplied from the VDD input VDD_CAP is equal to
VDD, under no load.
Note 4 – (100mV typ Hysteresis)
Summit Microelectronics, Inc
2086 2.1 12/13/2005
9
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
