SMS2902/SMS2904/SMS2916
PIN DESCRIPTIONS
Serial Clock (SCL)
- The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA)
- The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.
RESET#
- RESET# is an active low output. Whenever V
CC
is below V
TRIP
the SMS29xx will drive the RESET# pin to
ground. The RESET# pin is an I/O and can be used as a
reset input. Refer to Figure 1 as an example use of this pin
as a push button switch debounce circuit. It should be
noted this is an open drain output and an external pull-up
resistor tied to V
CC
is needed for proper operation.
RESET
— RESET is an active high output. Whenever V
CC
is below V
TRIP
the SMS29xx will drive the RESET pin to the
V
CC
rail. The RESET pin is an I/O and can be used as a
reset input. It should be noted this is an open drain output
and an external pull-down resistor tied to ground is needed
for proper operation.
WDI#
- The WDI# input is used as a hardware method of
clearing the watchdog timer. A high to low transition on this
pin will clear the watchdog timer. If a transition is not
detected within 1.6 seconds the watchdog will time out
and force the reset outputs active.
ENDURANCE AND DATA RETENTION
The SMS29xx is designed for applications requiring
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
erase/write cycles.
Reset Controller Description
The SMS29xx provides a precision RESET controller
that ensures correct system operation during brown-out
and power-up/-down conditions. It is configured with two
open drain RESET outputs; pin 7 is an active high output
and pin 2 is an active low output.
During power-up, the RESET outputs remain active until
V
CC
reaches the V
TRIP
threshold and will continue driving
the outputs for t
PURST
(200 msec) after reaching V
TRIP
.
The RESET outputs will be valid so long as V
CC
is > 1.0V.
During power-down, the RESET outputs will begin driv-
ing active when V
CC
falls below V
TRIP
.
The RESET pins are I/Os; therefore, the SMS29xx can
act as a signal conditioning circuit for an externally
applied reset. The inputs are edge triggered; that is, the
RESET input will initiate a reset timeout after detecting a
low to high transition and the RESET# input will initiate a
reset timeout after detecting a high to low transition. Refer
to the applications Information section for more details on
device operation as a reset conditioning circuit.
WATCHDOG TIMER OPERATION
The SMS29xx has a watchdog timer with a program-
mable timeout period. Whenever the watchdog times out
it will generate a reset output on both RESET# and
RESET.
Any transition on WDI will clear the watchdog timer. If a
transition is not detected within t
WDTO
seconds the watch-
dog will time out and force the reset outputs active.
2028 5.1 8/2/00
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SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
