SMS44
Longdog timer will generally be programmed to be of
longer duration than the watchdog and it will generate a
reset if it times out. Both timers are cleared by a low to high
transition on WLDI and they both start simultaneously.
If the watchdog should timeout the device status will be
recorded in the status register. If the Longdog times out
RESET# will drive low either until a WLDI clear is received
or until t
PRTO
(whichever occurs first), at which time it will
return high. Refer to Figures 3 and 4 illustrating the action
of RESET# and IRQ# with respect to the Watchdog and
Longdog timers and the WLDI input.
If WLDI is held low the timers will free-run generating a
series of interrupts and resets. If WLDI is held high the
interrupt (watchdog) output will be disabled and only the
reset (Longdog) output will be active.
When the Longdog times out, a reset will be generated.
When reset returns high (after t
PRTO
or after a WLDI
strobe) both timers are reset to time zero. Therefore, if the
Longdog t
PLDTO
is equal to or shorter than the watchdog
t
PWDTO
, the reset will effectively clear the interrupt before
it can drive the output low.
7
MSB
6
5
4
3
2
1
0
LSB
Address
Select
Lock AS0
x
x
0
0
1
x
x
PUP# State
PUP#3
1
0
PUP#2
1
0
PUP#1
1
0
Device type address 1010, responds
only to biased A2 & A1 combinations
Device type address 1011, responds
only to biased A2 & A1 combinations
Configuration read/write enabled
Configuration read/write locked out
2047 Table06 1.0
7
MSB
x
x
x
x
x
x
x
x
0
1
6
5
4
3
2
WD2
1
0
LSB
1
SEQ RTO1 RTO0 LD1 LD0
x
x
x
x
0
0
1
1
x
x
x
x
x
x
0
1
0
1
x
x
0
0
1
1
x
x
x
x
x
x
0
1
0
1
x
x
x
x
x
x
WD1 WD0
1600ms
3200ms
6400ms
Table 6. Configuration Register 7
Register 6 is also used to set the programmable reset
timeout period (t
PRTO
) and to select the sequence option.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
t
PDLY
X
0ms (no) Delay
25ms Delay
50ms Delay
100ms Delay
2047 Table07 1.0
Longdog Off
t
PRTO
= 25ms
t
PRTO
= 50ms
t
PRTO
= 100ms
t
PRTO
= 200ms
Sequence On
Sequence Off
2047 Table04 1.0
Table 7. PUP Delays
Sequence Delay Programming
The sequence delays are programmed in register 7. Bit 7
of register 6, must be set to a “0” in order to enable the
sequencing of the PUP# outputs. Sequencing will not
commence until V
0
is above its programmed threshold.
Each PUP# (-3, -2 and -1) is delayed according to the
states of its Bit 1 and Bit 0 as indicated in Table 7.
Refer to Figures 5 and 6 for the detailed timing relationship
of the programmable power-on sequencing.
Table 4. Configuration Register 6
7
MSB
0
LSB
0
1
0
1
0
1
6
5
4
3
LD0
2
1
SEQ RTO1 RTO0 LD1
WD2 WD1 WD0
0
0
1
1
1
1
0
1
0
0
1
1
OFF
400ms
800ms
1600ms
3200ms
6400ms
2047 Table05 1.0
Table 5. Configuration Register 6
8
2047 2.3 10/23/00
SUMMIT MICROELECTRONICS, Inc.
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
