SMS46
Preliminary Information
PIN DESCRIPTIONS
V
0
, V
1
, V
2
, V
3
(16, 2, 3, 14)
These inputs are used as the voltage monitor inputs and
as the voltage supply for the SMS46. Internally they are
actively diode ORed and the input with the highest voltage
potential will be the default supply voltage (VDD_CAP).
The RESET# outputs will be valid if any one of the four
inputs is above 1V. However, for full device operation at
least one of the inputs must be at 2.7V or higher.
The sensing threshold for each input is independently
programmable in 5mV increments from 0.6V to 1.875V or
15mV increments from 1.8V to 5.625V. Also, the occur-
rence of an under- or over-voltage condition that is detected
as a result of the threshold setting can be used to generate
a RESET#0-3. The programmable nature of the threshold
voltage eliminates the need for external voltage divider
networks.
GND
Power supply return.
MR# (1)
The manual reset input always generates a RESET#0-3
output whenever it is driven low. The duration of the
RESET# output pulse will be initiated when MR# goes low
and it will stay low for the duration of MR# low pulse plus
the programmed reset time-out period (t
PRTO
). MR# must
be held low during a configuration register write or read.
This signal is pulled up internally through a 50kΩ resistor.
RESET#0-3 (11, 4, 5, 13)
The reset outputs are active low open drain outputs. They
are driven low whenever the MR# input is low or whenever
a triggering under-voltage or over-voltage condition exists
on the corresponding input channel or when the Watchdog
timer expires. The four voltage monitor inputs are always
functioning, but their ability to generate a reset is program-
mable (configuration
register 4).
Refer to Figures 2, 3 and
5 for a detailed illustration of the relationship between MR#,
RESET#0-3 and the V
IN
levels.
VPTH-UV
V
0
— V
3
tPRTO
RESET#
tDRST
Figure 3 - RESET# Timing
VDD_CAP (12)
The VDD_CAP pin connects to the internal supply voltage
for the SMS46. A capacitor is placed on this pin to filter
supply noise as well as hold up the device in the event of
power failure. The voltage on this node is determined by the
highest input voltage. Loading of this pin should be
minimized to prevent excessive power dissipation in the
part.
WLDI (15)
Watchdog input. A low to high transition on the WLDI input
will clear the watchdog timer, effectively starting a new
time-out period. This signal is pulled up internally through
a 50kΩ resistor.
If WLDI is stuck low and no low-to-high transition is received
within the programmed t
PWDTO
period (programmed watch
dog time-out) the RESET#0-3 outputs will be driven low.
Holding WLDI high will not block the Watchdog from timing
out and generating a reset. Refer to Figure 4 for a detailed
illustration of the relationship between RESET#0-3 and
WLDI.
A1, A2 (6, 7)
A1 and A2 are the address inputs. When addressing the
SMS46 memory or configuration registers the address
inputs distinguish which one of four possible devices
sharing the common bus is being addressed.
SDA (9)
SDA is the serial data input/output pin. It should be tied to
V
DD_CAP
through a pull-up resistor.
MR#
tDMRRST
RESET#
tPRTO
Figure 2 - RESET# Timing with MR#
6
2083 1.1 06/04/04
SUMMIT MICROELECTRONICS, Inc.
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
