SMS46
Preliminary Information
I
2
C INTERFACE (CONTINUED)
The high order bits of the address byte remain constant.
Should the Master transmit more than 16 bytes, prior to
generating the Stop condition, the address counter will
rollover and the previously written data will be overwrit-
ten. As with the byte Write operation, all inputs are disabled
during the internal Write cycle. Refer to Figure 11 for the
address, Acknowledge, and data transfer sequence.
Master
SDA
Slave
S
T
A
R Device Type Bus
T Address Address
Typical Write Operation
(Standard memory device type)
A A A A A A A A
7 6 5 4 3 2 1 0
A
C
K
A
C
K
D D D D D D D D
7 6 5 4 3 2 1 0
A
C
K
S
T
O
P
1 0 1 0
R
B B
A A A /
2 1 8 W
Up to 15
additional bytes
can be written
before issuing
the stop.
N
A S
C T
K O
P
Master
SDA
Slave
S
T
A
R
T
Typical Reading Operation
(Alternate memory device type)
B B
R
A A A /
2 1 8 W
A
C
K
A A A A A A A A
7 6 5 4 3 2 1 0
S
T
A A
C R
K T
1 01 1
1 01 1
B B A R
A A
/
2 1 8 W
A
C
K
D D D D D D D D
7 6 5 4 3 2 1 0
Master
SDA
Slave
S
T
A
R
T
Writing Configuration Registers
R
B B
A A X /
W
2 1
A
C
K
S
T
O
P
D D D D D D D D
7 6 5 4 3 2 1 0
A
C
K
A
C
K
1 00 1
C C C C C C C C
7 6 5 4 3 2 1 0
Master
SDA
Slave
S
T
A
R
T
Reading the Configuration Register
B B
R
A A X /
2 1
W
A
C
K
C C C C C C C C
7 6 5 4 3 2 1 0
S
T
A A
C R
K T
N
A S
C T
K O
P
1 00 1
1 00 1
B B
R
A A X /
2 1
W
A
C
K
D D D D D D D D
7 6 5 4 3 2 1 0
2047 Fig11
Figure 9 - Read and Write Operations
SUMMIT MICROELECTRONICS, Inc.
2083 1.1 06/04/04
13
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
