SMS64
Preliminary
APPLICATIONS INFORMATION (CONTINUED)
Command Register
COMMAND REGISTER
7
6
5
4
3
2
1
0
The command register (slave address 1001
[BIN]
1 = WLDI
1 = FS
1 = PWR_DOWN
register address 0F [HEX]) contains 4 bits used for
software control of several functions in the SMS64
(see Figure 7). Each of these functions is activated by
writing a 1 to the function’s bit in the command register
(listed below). Only one command can be issued at a
1 = PWR_UP
Fault & Status Register
time; therefore, only data bytes 80[HEX], 40[HEX], 20[HEX]
,
5
4
3
2
1
0
10[HEX] and 00[HEX] should be written to the command
register. The command register is volatile and will be
cleared when power is removed.
UV/OVA
UV/OVB
UV/OVC
UV/OVD
UV/OVE
UV/OVF
Bit 7 is the power-on bit. When active it will initiate a
power-on sequence.
Bit 6 is the power-off bit. When active it will initiate a
power-off sequence.
Bit 5 is OR’ed with the FS# pin. When active it will
Figure 7 – Command and Status Registers
turn off all PUP outputs.
Bit 4 is OR’ed with the WLDI pin. When active it will
clear both the Longdog and Watchdog timers and
block interrupts.
For prototyping purposes, Summit can provide a
programming cable (SMX3200) that interfaces a PC
parallel port to the serial interface of the SMS64 (see
the ‘Development Hardware and Software’ section).
Summit provides software that can be downloaded
FAULT and STATUS REGISTERS
from its website without charge.
The software
The fault and status registers (see Figure 7) are
volatile registers which reflect the conditions of the VM
inputs. In either register a fault condition (under-
voltage or over-voltage) is represented as a “1”.
provides an intuitive graphical user interface
comprised of drop-down menus that make selecting
options straightforward, thereby eliminating the need
to understand the register configurations in detail.
The Fault register (located at register address 0D
[HEX]) latches the state of the VM inputs when an IRQ#
is generated.
MEMORY ARRAY
The SMS64 has 4-K bits of nonvolatile memory
that is accessible over the 2-wire serial interface. This
memory can be used in a dynamic manner by the host
processor or it could be used to store board
configuration information or board identification
information. The slave address used to access the
memory can be configured as 1010 [BIN] or 1011 [BIN].
The Status register (located at register address 0E
[HEX]) reflects the current state of the VM inputs.
CONFIGURATION REGISTERS
The SMS64 has 24 configuration registers that
allow programming voltage thresholds, timer values,
sequencing order and output configurations. All of
these registers are accessible over the I2C serial
interface.
The memory array can be read whenever chip
select is enabled (CS# low). In order to prevent
inadvertent writes, memory writes are blocked when
either RST_A# or RST_B# are active. Therefore, the
memory can only be written after the device has
performed a power-on operation, the reset outputs
(RST_A# and RST_B#) have timed out and before the
device has been issued a force shutdown or power-off
command. MR# must also be high.
Summit Microelectronics, Inc
2060 2.22 10/09/03
15
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
