HV2321
Truth Table
D0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D1
D2
D3
D4
D5
D6
D7
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CLR
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Hold Previous State
All Switches Off
SW0
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
SW1
SW2
SW3
SW4
SW5
SW6
SW7
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. D
OUT
is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
D
N–1
DATA
IN
5 0%
D
N
50%
D
N+1
LE
50%
50%
t
WLE
t
SD
CLOCK
t
SU
DATA
O UT
50%
t
h
t
DO
50%
t
OFF
50%
t
ON
OFF
V
OUT
(TYP )
ON
5 0%
t
WCL
5 0%
90%
1 0%
CLR
5
SUPERTEX [ Supertex, Inc ]
