HV508
Truth Table
HV
EN
H
H
L
L
POL
H
L
H
L
HV
OUT1
HV
IN
GND
LV
IN
GND
HV
OUT2
GND
HV
IN
GND
LV
IN
Timing Diagram
V
IH
POL
50%
50%
V
IL
V
IN
or LV
IN
5%
t
(ON)
t
(OFF)
HV
OUT1
GND
80%
Figure 1
V
IH
HV
EN
50%
V
IL
HV
IN
HV
OUT1
LV
IN
t
EN(ON)
80%
Figure 2
Block Diagram
LV
IN
HV
IN
V
DD
Level
Translator
HV
OUT
1
Level
Translator
CMOS
Logic
HV
EN
POL
GND
Level
Translator
HV
OUT
2
Level
Translator
12/13/010
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