HV5522/HV5530/HV5622/HV5630
Functional Block Diagram
Polarity
Blanking
Latch Enable
HV
OUT
1
Data Input
Clock
Latch
32-Bit
Shift
Register
Latch
HV
OUT
2
(Outputs 3 to 30
not shown)
HV
OUT
31
Latch
HV
OUT
32
Data Out
Latch
Function Table
Inputs
Function
All on
All off
Invert mode
Load S/R
Load
Latches
Transparent
Latch mode
Data
X
X
X
H or L
X
X
L
H
CLK
X
X
X
↓
LE
X
X
L
L
↑
↑
BL
L
L
H
H
H
H
H
H
POL
L
H
L
H
H
L
H
H
Shift Reg
1 2…32
*
*
*
*…*
*…*
*…*
Outputs
HV Outputs
1
2…32
On
Off
*
*
*
*
Off
On
On…On
Off…Off
*…*
*…*
*…*
*…*
*…*
*…*
Data Out
*
*
*
*
*
*
*
*
*
H or L *…*
*
*
L
H
*…*
*…*
*…*
*…*
H or L
H or L
↓
↓
H
H
Notes:
H = high level, L = low level, X = irrelevant,
↓
= high-to-low transition,
↑
= low-to-high transistion.
* = dependent on previous stage’s state before the last CLK
↓
or last LE high.
4
SUPERTEX [ Supertex, Inc ]
