HV6810
Pin Descriptions
HV6810 20-J Lead PLCC (PJ)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Function
Q8
Q7
Q6
CLOCK
N/C
VSS
VDD
LE (STROBE)
Q5
Q4
Q3
Q2
Q1
BLANKING
DATA IN
N/C
VBB
SERIAL DATA OUT
Q10
Q9
When blanking is low, all Q’s are forced to a high state, regardless of data in each
channel. When OL is low, all Q’s are forced to a low state, regardless of data in
each channel.
Input data for the input shift register.
No connection.
High voltage power supply.
Output data from the shift register.
High voltage output.
High voltage output.
Input data are shifted into the data shift register on the thepostive edge of the
clock.
No connection.
Usually V
SS
= 0, ground connection.
Low voltage power supply.
When LE is high, data is transferred from data shift register to the Q output latch.
When LE is low, data is latched into data latches and new data can be clocked into
the shift register.
High voltage output.
Description
5
SUPERTEX [ Supertex, Inc ]
