HV9105/HV9108
Technical Description
Preregulator
The preregulator/startup circuit for the HV9105/08 consists of a
high-voltage N-channel depletion-mode DMOS transistor driven
by an error amplifier to form a controlled current path between the
V
IN
terminal and the V
DD
terminal of the HV9105/08. Maximum
current (about 20 mA) occurs when V
DD
= 0, with current reducing
as V
DD
rises. This path shuts off altogether when V
DD
rises to
somewhere between 7.8 and 9.4V, so that if V
DD
is held at 10 or
12V by an external source (generally the supply the chip is
controlling) no current other than leakage is drawn through the
high voltage transistor. This minimizes dissipation.
An external capacitor between V
DD
and V
SS
is generally required
to store energy used by the chip during the time between shutoff
of the high voltage path and the V
DD
supply’s output rising enough
to take over the powering of the chip. This capacitor generally also
serves as the output filter capacitor for that output from the supply.
1.0µF is generally sufficient to assure against double-starting.
Capacitors as small as 0.1µF can work when faster response from
the V
DD
line is required. The chosen capacitor should have very
good high frequency characteristics and be mounted so that the
sum of the lead length between capacitor and IC for both leads is
less than 2.5 cm. Stacked polyester or ceramic capacitors work
well. Electrolytic capacitors are generally not suitable.
A common resistor divider string is used to monitor V
DD
for both
the undervoltage lockout circuit and the shutoff circuit of the high
voltage FET. Setting the undervoltage sense point about 0.6V
lower on the string than the FET shutoff point guarantees that the
undervoltage lockout always releases before the FET shuts off.
Reference
The reference section of the HV9105/08 consists of a stable
bandgap reference followed by a buffer amplifier which scales the
voltage up to approximately 4.0V. The scaling resistors of the
reference buffer amplifier are trimmed during manufacture so that
the output of the error amplifier when connected in a gain of -1
configuration is as close to 4.000V as possible. This nulls out any
input offset of the error amplifier. As a consequence, even though
the observed reference voltage of a specific part may not be
exactly 4.0V, the feedback voltage required for proper regulation
will be 4.0V.
A resistor of approximately 50KΩ is placed internally between the
output of the reference buffer amplifier and the circuitry it feeds
(reference output pin and non-inverting input to the error ampli-
fier). This allows overriding the internal reference with a low-
impedance voltage source
≤6.0V.
In general, because the refer-
ence voltage of the Supertex HV9105/08 is not noisy, as some
previous devices have been, overriding the reference should
seldom be necessary.
Because the reference is a high impedance node, and usually
there will be significant electrical noise near it, a bypass capacitor
between the reference pin and V
SS
is strongly recommended. The
reference buffer amplifier is intentionally compensated to be
stable with a capacitive load of 0.01 to 0.1µF.
Error Amplifier
The error amplifier is a true low-power differential input opera-
tional amplifier intended for around-the-amplifier compensation.
It is of mixed CMOS-bipolar construction: a PMOS input stage is
used so the common-mode range includes ground and the input
impedance is very high. This is followed by bipolar gain stages
which provide high gain without the electrical noise of all-MOS
amplifiers. The amplifier is unity-gain stable.
Bias Circuit
An external bias resistor, connected between the bias pin and V
SS
is required by the HV9105/08 to set currents in a series of current
mirrors used by the analog sections of the chip. Nominal external
bias current requirement is 7.5µA, which can be set by a 820KΩ
to 1.3MΩ resistor if a 10V V
DD
is used, or a 1.2MΩ to 2.0MΩ
resistor if a 12V V
DD
is used. A precision resistor is NOT required;
±
5% is fine.
For extremely low power operation, the value of bias current can
be reduced to as low as 4.0µA by further increases in the value of
the bias resistor.
Current Sense Comparators
The HV9105/08 uses a true dual comparator system with inde-
pendent comparators for modulation and current limiting. This
allows the designer greater latitude in compensation design, as
there are no clamps (except ESD protection) on the compensa-
tion pin. Like the error amplifier, the comparators are of low-noise
BiCMOS construction.
Clock Oscillator
The clock oscillator of the HV9105/08 consists of a ring of CMOS
inverters, timing capacitors, a capacitor discharge FET, and, in
the 50% maximum duty cycle version, a frequency dividing flip-
flop. A single external resistor between the OSC In and OSC Out
pins is required to set oscillator frequency (see Fig. 4). For the
50% maximum duty cycle versions the ‘Discharge’ pin is internally
connected to GND. For the 99% duty cycle version, ‘Discharge’
can either be connected to V
SS
directly or connected to V
SS
through a resistor used to set a deadtime.
One difference exists between the Supertex HV9105/08 and
competitive 9105 parts. The oscillator of the Supertex HV9105/08
is shut off when a shutoff command is received. This saves about
100µA of quiescent current, which aids in the construction of
power supplies to meet CCITT specification I.430, and in other
situations where an absolute minimum of quiescent power dissi-
pation is required.
Remote Shutdown
The shutdown and reset pins can be used to perform either
latching or non-latching shutdown of a converter as required.
These pins have internal current source pull-ups so they can be
driven from open-drain logic. When not used, they should be left
open, or connected to V
DD
.
Main Switch
The main switch is a normal N-channel power MOSFET. Unlike
the situation with competitive devices, the body diode can be used
if desired without destroying the chip.
6
SUPERTEX [ Supertex, Inc ]
