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SM59A16U1U48VP 参数 Datasheet PDF下载

SM59A16U1U48VP图片预览
型号: SM59A16U1U48VP
PDF下载: 下载PDF文件 查看货源
内容描述: SM59A16U1 8位微控制器 64KB具有ISP闪存 & 6K + 256B RAM嵌入式 [SM59A16U1 8-Bit Micro-controller 64KB with ISP Flash & 6K+256B RAM embedded]
分类和应用: 闪存微控制器
文件页数/大小: 146 页 / 4372 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
The error flag is reset only if:
Phase two finished (arithmetic operation successful completed) and read access to MDx
registers.
MDOV: Multiplication Division Overflow flag. The overflow flag is read only.
The overflow flag is set when:
Division by Zero
Multiplication with a result greater then 0000FFFFh
Start of normalizing if the most significant bit of MD3 is set(MD3.7=1)
The overflow flag is reset when:
Write access to MD0 register(Start Phase one)
SLR: Shift direction bit.
SLR = 0 – shift left operation.
SLR = 1 – shift right operation.
SC[4:0]: Shift counter.
When preset with 00000b, normalizing is selected. After normalize sc.0 – sc.4 contains
the number of normalizing shifts performed. When sc.4 – sc.0 ≠ 0, shift operation is
started. The number of shifts performed is determined by the count written to sc.4 to
sc.0.
sc.4 – MSB ... sc.0 – LSB
6.2
Operation of the MDU
The operation of the MDU consists of three phases:
6.2.1
First phase: loading the MDx registers, x = 0~5:
The type of calculation the MDU has to perform is selected following the order in which the mdx registers are written to.
Operation
First write
Last write
32bit/16bit
MD0 Dividend Low
MD1 Dividend
MD2 Dividend
MD3 Dividend High
MD4 Divisor Low
MD5 Divisor High
Table 6-2: MDU registers write sequence
16bit/16bit
16bit x 16bit
MD0 Dividend Low
MD0 Multiplicand Low
MD1 Dividend High
MD4 Multiplicator Low
MD1 Multiplicand High
MD4 Divisor Low
MD5 Divisor High
shift/normalizing
MD0 LSB
MD1
MD2
MD3 MSB
ARCON start conversion
MD5 Multiplicator High
A write to md0 is the first transfer to be done in any case. Next writes must be done as shown in Table 6-1 to determine
MDU operation. Last write finally starts selected operation.
6.2.2
Second phase: executing calculation.
During executing operation, the MDU works on its own parallel to the CPU. When MDU is finished, the MDUF register
will be set to one by hardware and the flag will clear at next calculation.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071
Ver A
SM59A16U1
04/12/2013
- 43 -