SM59R16A5L25 参数 Datasheet PDF下载

SM59R16A5/SM59R09A5/SM59R05A5

8-Bit Micro-controller

64KB/36KB/20KB with ISP Flash

& 2KB RAM embedded

2. Instruction Set

All SM59R16A5 instructions are binary code compatible and perform the same functions as they do with the industry

standard 8051. The following tables give a summary of the instruction set cycles of the SM59R16A5 Microcontroller core.

Mnemonic

ADD A,Rn

ADD A,direct

ADD A,@Ri

ADD A,#data

ADDC A,Rn

ADDC A,direct

ADDC A,@Ri

ADDC A,#data

SUBB A,Rn

SUBB A,direct

SUBB A,@Ri

SUBB A,#data

INC A

INC Rn

INC direct

INC @Ri

INC DPTR

DEC A

DEC Rn

DEC direct

DEC @Ri

MUL AB

DIV

DA A

Table 2-1: Arithmetic operations

Description

Add register to accumulator

Add direct byte to accumulator

Add indirect RAM to accumulator

Add immediate data to accumulator

Add register to accumulator with carry flag

Add direct byte to A with carry flag

Add indirect RAM to A with carry flag

Add immediate data to A with carry flag

Subtract register from A with borrow

Subtract direct byte from A with borrow

Subtract indirect RAM from A with borrow

Subtract immediate data from A with borrow

Increment accumulator

Increment register

Increment direct byte

Increment indirect RAM

Increment data pointer

Decrement accumulator

Decrement register

Decrement direct byte

Decrement indirect RAM

Multiply A and B

Divide A by B

Decimal adjust accumulator

Code

28-2F

25

26-27

24

38-3F

35

36-37

34

98-9F

95

96-97

94

04

08-0F

05

06-07

A3

14

18-1F

15

16-17

A4

84

D4

Bytes

1

2

1

2

1

2

1

2

1

2

1

2

1

1

2

1

1

1

1

2

1

1

1

1

Cycles

1

2

2

2

1

2

2

2

1

2

2

2

1

2

3

3

1

1

2

3

3

5

5

1

Specifications subject to change without notice contact your sales representatives for the most recent information.

ISSFD-M047

18

Ver.G SM59R16A5 01/2014