SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
6. Multiplication Division Unit (MDU)
This on-chip arithmetic unit provides 32-bit division, 16-bit multiplication, shift and normalize features, etc. All operations
are unsigned integer operations.
Mnemonic
PCON
ARCON
MD0
MD1
MD2
MD3
MD4
MD5
6.1.
Description
Power control
Arithmetic Control
register
Multiplication/Divi
sion Register 0
Multiplication/Divi
sion Register 1
Multiplication/Divi
sion Register 2
Multiplication/Divi
sion Register 3
Multiplication/Divi
sion Register 4
Multiplication/Divi
sion Register 5
Direct
87H
EFh
E9h
EAh
EBh
ECh
EDh
EEh
Bit 6
Bit 5
Bit 4
Multiplication Division Unit
SMOD MDUF
-
-
MDEF
MDOV
SLR
MD0[7:0]
MD1[7:0]
MD2[7:0]
MD3[7:0]
MD4[7:0]
MD5[7:0]
Bit 7
Bit 3
-
Bit 2
-
SC[4:0]
Bit 1
STOP
Bit 0
IDLE
RESET
40H
00H
00H
00H
00H
00H
00H
00H
Operating registers of the MDU
The MDU is handled by seven registers, which are memory mapped as special function registers. The arithmetic unit
allows operations concurrently to and independent of the CPU’s activity. Operands and results registers are MD0 to MD5.
Control register is ARCON. Any calculation of the MDU overwrites its operands.
Mnemonic: ARCON
7
6
5
MDEF MDOV
SLR
4
3
2
SC[4:0]
1
Address: EFh
0
Reset
00H
MDEF: Multiplication Division Error Flag.
The MDEF is an error flag. The error flag is read only. The error flag indicates an
improperly performed operation (when one of the arithmetic operations has been
restarted or interrupted by a new operation). The error flag mechanism is automatically
enabled with the first write to MD0 and disabled with the final read instruction from MD3
multiplication or shift/normalizing) or MD5 (division) in phase three.
The error flag is set when:
1. Phase two in process and write access to mdx registers (restart or interrupt
calculations)
The error flag is reset only if:
Phase two finished (arithmetic operation successful completed) and read access to MDx
registers.
MDOV: Multiplication Division Overflow flag. The overflow flag is read only.
The overflow flag is set when:
1. Division by Zero
2. Multiplication with a result greater then 0000FFFFh
3. Start of normalizing if the most significant bit of MD3 is set(MD3.7=1)
The overflow flag is reset when:
Write access to MD0 register(Start Phase one)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
32
Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
