SyncMOS Technologies International, Inc.
TA= -40℃ to +85℃
C
L
=100pF for Port0, ALE and /PSEN; C
L
=80pF for all other outputs unless otherwise specified.
Symbol
FIGURE
PARAMETER
External Clock drive into XTAL1
tCLK
4
tCLKH
4
tCLKL
4
tCLKR
4
tLLIV
4
tCYC
4
NOTES:
1. Operating at 25MHz.
Xtal1 Period
Xtal1 HIGH time
Xtal1 LOW time
XTAL1 rise time
XTAL1 fall time
Controller cycle time = tCLK / 4
40(1)
20
20
-
-
3.33
-
-
-
10
10
-
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & RTC & ADC & PWM & PDWU embedded
MIN
MAX
UNIT
ns
ns
ns
ns
ns
Ns
Symbol
1/tCLK
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
tAVLL
tLLAX
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
FIGURE
7
7
7
7
7
7
7
7
7
7
7
7
8,9
8,9
8
9
8
8
8
8
8
8,9
8,9
9
9
9
8
8,9
10
10
10
10
10
PARAMETER
Program Memory
System clock frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE LOW to valid instruction in
ALE LOW to /PSEN LOW
/PSEN pulse width
/PSEN LOW to valid instruction in
Input instruction hold after /PSEN
Input instruction float after /PSEN
Address to valid instruction in
/PSEN low to address float
MIN
3.0
2tCLK-40
tCLK-40
tCLK-30
tCLK-30
3tCLK-45
MAX
25
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4tCLK-100
3tCLK-105
0
tCLK -25
5tCLK-105
10
tCLK-40
tCLK-35
6tCLK-100
6tCLK-100
5tCLK-165
0
2tCLK-70
8tCLK-150
9tCLK-165
3tCLK+50
Data Memory
Address valid to ALE LOW
Address hold after ALE LOW
/RD pulse width
/WR pulse width
/RD LOW to valid data in
Data hold after /RD
Data float after /RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to /RD or /WR LOW
Address valid to /WR or /RD LOW
Data valid to /WR transition
Data before /WR
Data hold after /WR
/RD LOW to address float
/RD or /WR HIGH to ALE HIGH
3tCLK-50
4tCLK-130
tCLK-50
7tCLK-150
tCLK-50
tCLK-40
12tCLK
10tCLK-133
2tCLK-117
0
0
tCLK+40
UART
Serial port clock time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10tCLK-133
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.1 SM89S16R1 08/2006
10
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
