Technical Specification
MECHANICAL DIAGRAM
Top View
0.950 (24.13)
2.30
(58.42)
0.150 0.150 0.150
(3.81) (3.81) (3.81)
Input:
Outputs:
Current:
Package:
36-75 V
5.0 V/ 3.3 V
10 A
Quarter-brick
0.100
(2.54)
0.200
(5.08)
0.200
(5.08)
1.45 0.200
(36.83) (5.08)
0.200
(5.08)
0.200
(5.08)
0.225
(5.72)
1
2
3
4
5
6
7
18 17 16 15
14
13
12
11
10
9
8
0.150
(3.81)
0.150
(3.81)
2.00
(50.8)
Bottom side
Clearance
0.064 ±0.028
(1.63 ±0.71)
Side View
Overall
Height
0.54 (13.7)
See Note 2
1.45
(36.83)
Load Board
Flanged Pin
See Note 8
Lowest
Component
NOTES
1) All Pins are 0.040" (1.02 mm) diameter with 0.080" (2.03 mm)
diameter standoff shoulders.
2) Other pin extension lengths available. Recommended pin
length is 0.03" (0.76 mm) greater than the PCB thickness.
3) All Pins: Material - Copper Alloy
Finish - Matte Tin over Nickel plate
4) Undimensioned components are shown for visual reference only.
5) All dimensions in inches (mm)
Tolerances: x.xx +0.02" (x.x +0.5 mm)
x.xxx +0.010" (x.xx +0.25 mm)
6) Weight: 1.2 oz (34 g) typical
7) Workmanship: Meets or exceeds IPC-A-610C Class II
8) The flanged pins are designed to permit surface mount soldering
(allowing to avoid the wave soldering process) through the use of
the flanged pin-in-paste technique.
PIN DESIGNATIONS
Negative A Feed (Externally Fused)
Negative B Feed (Externally Fused)
Positive A Feed (Externally Fused)
Positive B Feed (Externally Fused)
Enable A Input (Externally Fused)
(Short Pin Tied to VRTN_A on Backplane)
Enable B Input (Externally Fused)
(Short Pin Tied to VRTN_B on Backplane)
Shelf Ground
5.0V (Relative to LOGIC_GND)
3.3V (Relative to LOGIC_GND)
I
2
C Address Input *
(Connect External Resistor to LOGIC_GND) **
I
2
C Data (Relative to LOGIC_GND) *
I
2
C Clock (Relative to LOGIC_GND) *
Logic Ground
Isolated A/B Feed Loss or Open Fuse Alarm
(Relative to LOGIC_GND)
Negative Output to Payload Power Converter
Hold-Up Voltage Trim
(Connect External Resistor to -48V_OUT)
Positive Output to Payload Power Converter
Positive Connection to Hold-Up Capacitor
(Negative Connection to -48V_OUT)
05/04/09
Page 2
Pin No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
-48V_A
-48V_B
VRTN_A
VRTN_B
ENABLE_A
ENABLE_B
SHELF_GND
5.0V
3.3V
I2C_ADR
I2C_DAT
I2C_CLK
LOGIC_GND
ALARM
-48V_OUT
HU_TRIM
VRTN_OUT
HU_CAP
Function
* Pins 10, 11, and 12 are only available on the full feature version.
See the ordering page for more information.
** Single resistor connected externally to LOGIC_GND selects the three
least significant bits of I
2
C Address “0101xxx”.
Product # IQ65033QMA10
Phone 1-888-567-9596
17
18
www.synqor.com
Doc.# 005-IQ5033S Rev. G
SYNQOR [ SYNQOR WORLDWIDE HEADQUARTERS ]
