MQFL-28VE-1R8S
Output:
1.8V
Current:
40A
technical Specification
Inside the converter, +SENSE is connected to +Vout with a resistor
value from 100W to 301W, depending on output voltage, and
–SENSE is connected to OUTPUT RETURN with a 10W resistor
It is also important to note that when remote sense is used, the
voltage across the converter’s output terminals (pins 7 and 8)
will be higher than the converter’s nominal output voltage due
to resistive drops along the connecting wires. This higher volt-
age at the terminals produces a greater voltage stress on the
converter’s internal components and may cause the converter to
fail to deliver the desired output voltage at the low end of the
input voltage range at the higher end of the load current and
temperature range. Please consult the factory for details.
SYNCHRONIZATION:
The MQFL converter’s regulation and
isolation stage switching frequencies can be synchronized to an
external frequency source that is in the 500 kHz to 600 kHz
range. The boost-converter stage is free-running at about 670
kHz while it is operational, and is not affected by synchroniza-
tion signals. A pulse train at the desired frequency should be
applied to the SYNC IN pin (pin 6) with respect to the INPUT
RETURN (pin 2). This pulse train should have a duty cycle in the
20% to 80% range. Its low value should be below 0.8V to be
guaranteed to be interpreted as a logic low, and its high value
should be above 2.0V to be guaranteed to be interpreted as a
logic high. The transition time between the two states should be
less than 300ns.
If the MQFL converter is not to be synchronized, the SYNC IN pin
should be left open circuit. The converter will then operate in its
free-running mode at a frequency of approximately 550 kHz.
Figure B shows the equivalent circuit looking into the SYNC IN
pin. Figure C shows the equivalent circuit looking into the SYNC
OUT pin.
5V
ad
pu
va
bl
ic n
at ce
io d
n
5K
PIN 6
PIN 2
SYNC IN
IN RTN
5K
TO SYNC
CIRCUITRY
n
Figure B:
Equivalent circuit looking into the SYNC IN pin with
respect to the IN RTN (input return) pin.
5V
5K
FROM SYNC
CIRCUITRY
SYNC OUT
PIN 5
PIN 2
IN RTN
OPEN COLLECTOR
OUTPUT
Figure C:
Equivalent circuit looking into SYNC OUT pin with
respect to the IN RTN (input return) pin.
If, due to a fault, the SYNC IN pin is held in either a logic low
or logic high state continuously, the MQFL converter will revert
to its free-running frequency.
The MQFL converter also has a SYNC OUT pin (pin 5). This
output can be used to drive the SYNC IN pins of as many as ten
(10) other MQFL converters. The pulse train coming out of SYNC
OUT has a duty cycle of 50% and a frequency
1 +VIN
that matches the
switching frequency of the converter with which it is associated.
2
This frequency is either the free-running frequency
IN
there is no
if
RTN
synchronization signal at the SYNC IN pin, or
3
synchroniza-
the
CASE
tion frequency if there is.
28Vdc –
ENA 1
The SYNC OUT signal is available only when the voltage at the
STABILITY pin (pin 3) is above approximately
5
12V and when
SYNC
inhibit
the converter is not inhibited through the ENA1 pin. An
OUT
open
6
through the ENA2 pin will
means
turn the SYNC OUT signal off.
not
on
CURRENT SHARE:
When several MQFL converters are placed
in parallel to achieve either a higher total load power or N+1
redundancy, their SHARE pins (pin 11) should be connected
together. The voltage on this common SHARE node represents the
average current delivered by all of the paralleled converters. Each
converter monitors this average value and adjusts itself so that its
output current closely matches that of the average.
ENA
Since the SHARE pin is
2
monitored with respect to the OUTPUT
11
RETURN (pin 8) by each converter, it is important to connect all of
SHARE
the converters’ OUTPUT RETURN pins together through a low DC
and AC impedance.
SNS 10
is done correctly, the converters
+
When this
will deliver their appropriate fraction of the total load current to
Rtrim
9
within +/- 10% at full rated load.
– SNS
12
+
4
SYNC IN
NOTE: An MQFL converter that has its SYNC IN pin driven by
the SYNC OUT pin of a second MQFL converter will have its
start of its switching cycle delayed approximately 180 degrees
relative to that of the second converter.
Whether or not converters are paralleled, the voltage at the
OUT RTN
Load
SHARE pin could be used
7
monitor the approximate average
to
+VOUT
current delivered by the converter(s). A nominal voltage of 1.0V
+
represents zero current and a nominal voltage of 2.2V represents
the maximum rated current, with a linear relationship in between.
The internal source resistance of a converter’s SHARE pin signal is
2.5 kW. During an input voltage fault or primary disable event, the
SHARE pin outputs a power failure warning pulse. The SHARE pin
will go to 3V for approximately 14ms as the output voltage falls.
Doc.# 005-0005206 Rev. 1
04/22/09
8
–
Product # MQFL-28VE-1R8S
Phone 1-888-567-9596
www.synqor.com
Page 12
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