ADC101S051
Block Diagram
20144707
Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
3
DIGITAL I/O
4
5
6
POWER SUPPLY
1
2
PAD
V
A
GND
GND
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source
and bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located
within 1 cm of the power pin.
The ground return for the supply and signals.
For package suffix CISD(X) only, it is recommended that the center pad should be
connected to ground.
SCLK
SDATA
CS
Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on falling edges of
the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins.
V
IN
Analog input. This signal can range from 0V to V
A
.
Symbol
Description
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2
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
