C2510Fx / CC2511Fx
13.7 MAC Timer (Timer 2)
The MAC timer is designed for slot timing
operations used by the MAC layer in an RF
protocol. The timer includes a highly tunable
prescaler allowing the user to select a timer
interval that equals, or is an integer fraction of,
a transmission slot.
•
8-bit timer
•
18-bit tunable prescaler
13.7.1
Timer Operation
the 18 bit counter and thus set the maximum
value.
The timer 2 interval / time slot, T, can be given
as:
T =
· Val(T2CTL.TIP)/ timer tick speed,
where the function Val(x) is set by
and defined as
Val(00) = 64
Val(01) = 128
Val(10) = 256
Val(11) = 1024
Example:
= 0x09
= 10
= 101 (812.5 kHz @ when
f
xosc
= 26 MHz)
T = 9 · 256 / 812.5 kHz = 2.84 ·10
-3
s
13.7.2
Timer 2 DMA Trigger
This section describes the operation of the
timer.
The timer count can be read from the
T2CT
SFR. At each active clock edge, the timer
count is decremented by one. When the timer
count reaches 0x00, the register bit
T2CTL.TEX
is set to 1. When
the timer will not wrap around when the timer
count reaches 0x00. When
timer count will wrap around and start counting
down from 0xFF.
If
will also be
asserted when
is set to 1. An
interrupt request will be generated if both
and
are set to 1.
When a new value is written to the timer count
register,
this value is stored in the
counter immediately. If an active clock edge
and a write to
occur at the same time,
the written value will be decremented before it
is stored.
The 18 bit prescaler is controlled by:
•
Timer tick speed (CLKCON.TICKSPD)
•
•
Prescaler value (T2PR)
All events in timer 2 are aligned to timer tick
speed
given
by
defines how fast the prescaler
counter counts up towards its maximum value
where it is reset and starts over again. The
prescaler value,
defines the 8 MSB of
There is one DMA trigger associated with
Timer 2. This is the DMA trigger T2_OVFL,
which is generated when
is set to
1.
13.7.3
Timer 2 Registers
The SFRs associated with Timer 2 are listed in
this section. These registers are the following:
•
– Timer 2 Control
•
– Timer 2 Prescaler
•
– Timer 2 Count
Note: These registers will be in their reset
state when returning to active mode from
PM2 and PM3.
SWRS055D
Page 123 of 243
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