C2510Fx / CC2511Fx
9
Circuit Description
RESET
HIGH SPEED
CRYSTAL OSC
(24 – 27 MHz)
32.768 kHz
CRYSTAL OSC
DEBUG
INTERFACE
HIGH SPEED
RC-OSC
CODE
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
IRQ
CTRL
FLASH CTRL
DMA
UNIFIED
FLASH
32 KB
FLASH
8051 CPU
CORE
XDATA
DATA
SFR
MEMORY
ARBITRATOR
USB BUS
USB
4 KB
SRAM
USB PHY
LOW PWR
RC-OSC
RESET_N
XOSC_Q2
XOSC_Q1
P2_4
P2_3
P2_2
P2_1
P2_0
WATCHDOG TIMER
ON-CHIP VOLTAGE
REGULATOR
VDD (2.0 - 3.6 V)
DCOUPL
DIGITAL
ANALOG
MIXED
POWER ON RESET
SFR bus
CLOCK MUX &
CALIBRATION
SLEEP TIMER
POWER MGT. CONTROLLER
1 KB
FIFO SRAM
DP
DM
RAM
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
SFR bus
P0_0
SYNTH
I/O CONTROLLER
I2S
AES
ENCRYPTION &
DECRYPTION
RADIO / I2S REGISTERS
ADC
AUDIO / DC
RADIO DATA INTERFACE
USART 0
USART 1
TIMER 1 (16-bit) +
Module
RECEIVE
CHAIN
FREQUENCY
SYNTHESIZER
TRANSMIT
CHAIN
TIMER 2 (8-bit MAC Timer)
TIMER 3 (8-bit)
TIMER 4 (8-bit)
RF_P
RF_N
Figure 9:
C C2510Fx/CC2511Fx
Block Diagram
A block diagram of
CC2510Fx/CC2511Fx
is
shown in Figure 9. The modules can be
divided into one out of three categories: CPU-
related modules, radio-related modules, and
modules related to power, test, and clock
distribution. In the following subsections, a
short description of each module that appears
in Figure 9.
SWRS055D
FRAME CONTROL
AGC
DEMODULATOR
MODULATOR
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