C2510Fx / CC2511Fx
XDATA
Register
Description
Retention6
Address
0xDF13
0xDF14
0xDF15
0xDF16
0xDF17
0xDF18
0xDF19
0xDF1A
0xDF1B
0xDF1C
0xDF1D
0xDF1E
0xDF1F
MCSM1
Main Radio Control State Machine configuration
Main Radio Control State Machine configuration
Frequency Offset Compensation configuration
Bit Synchronization configuration
AGC control
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
Y
Y
MCSM0
FOCCFG
BSCFG
AGCTRL2
AGCTRL1
AGCTRL0
FREND1
FREND0
FSCAL3
FSCAL2
FSCAL1
FSCAL0
AGC control
AGC control
Front end RX configuration
Front end TX configuration
Frequency synthesizer calibration
Frequency synthesizer calibration
Frequency synthesizer calibration
Frequency synthesizer calibration
Reserved
0xDF20
-
0xDF22
0xDF23
0xDF24
0xDF25
TEST2
TEST1
TEST0
Various Test Settings
Various Test Settings
Various Test Settings
Reserved
Y
Y
Y
Y
0xDF27
-
0xDF2D
0xDF2E
0xDF2F
0xDF30
0xDF31
0xDF36
0xDF37
0xDF38
0xDF39
0xDF3A
0xDF3B
0xDF3C
0xDF3D
PA_TABLE0
IOCFG2
PA output power setting
Radio test signal configuration (P1_7)
Radio test signal configuration (P1_6)
Radio test signal configuration (P1_5)
Chip ID[16:8]
Y
Y
IOCFG1
Y
IOCFG0
Y
PARTNUM
VERSION
FREQEST
LQI
NA
NA
NA
NA
NA
NA
NA
NA
Chip ID[7:0]
Frequency Offset Estimate
Link Quality Indicator
RSSI
Received Signal Strength Indication
Main Radio Control State
Packet status
MARCSTATE
PKSTATUS
VCO_VC_DAC PLL calibration current
Table 32: Overview of RF Registers
11.2.3.5 I2S Registers
0xDF48. Table 33 gives a descriptive overview
of these registers. Each register is described in
detail in Section 13.15.13, starting on Page
167.
The I2S registers are all related to I2S
configuration and control. The I2S registers can
only be accessed through XDATA memory
space and reside in address range 0xDF40 -
XDATA
Register
Description
Retention7
Address
SWRS055D
Page 48 of 243
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
