C2510Fx / CC2511Fx
3
3.1
Key Features (in more details)
High-Performance and Low-Power
8051-Compatible Microcontroller
•
Optimized 8051 core which typically
gives 8x the performance of a standard
8051
•
Two data pointers
•
In-circuit interactive debugging is
supported by the IAR Embedded
Workbench through a simple two-wire
serial interface
3.6
3.5
•
Typically used to connect to external
DAC or ADC
Hardware AES Encryption/Decryption
•
128-bit AES supported in hardware
coprocessor
Peripheral Features
•
Powerful DMA Controller
•
Power On Reset/Brown-Out Detection
•
ADC with eight individual input
channels, single-ended or differential
(
CC2511Fx
has six channels) and
configurable resolution
•
Programmable watchdog timer
•
Five timers: one general 16-bit timer
with DSM mode, two general 8-bit
timers, one MAC timer, and one sleep
timer
•
Two
programmable
USARTs
for
master/slave SPI or UART operation
•
21 configurable general-purpose digital
I/O-pins (
CC2511Fx
has 19)
•
Random number generator
3.7
Low Power
•
Four flexible power modes for reduced
power consumption
•
System can wake up on external
interrupt or when the Sleep Timer
expires
•
where external interrupts or the Sleep
Timer can wake up the system
•
where external interrupts can wake up
the system
•
Low-power fully static CMOS design
•
System clock source is either a high
speed crystal oscillator (24 – 27 MHz for
CC2510Fx
and 48 MHz for
CC2511Fx
) or a
high speed RC oscillator (12 – 13.5 MHz
for
CC2510Fx
and 12 MHz for
CC2511Fx
).
The high speed crystal oscillator must
be used when the radio is active.
3.2
8/16/32 kB Non-volatile Program
Memory and 1/2/4 kB Data Memory
•
8, 16, or 32 kB of non-volatile flash
memory,
in-system
programmable
through a simple two-wire interface or
by the 8051 core
•
Minimum flash memory
1000 write/erase cycles
endurance:
•
Programmable read and write lock of
portions of flash memory for software
security
•
1, 2, or 4 kB of internal SRAM
3.3
Full-Speed USB Controller (
CC2511Fx
)
•
5 bi-directional endpoints in addition to
control endpoint 0
•
Full-Speed, 12 Mbps transfer rate
•
Support for Bulk, Interrupt,
Isochronous endpoints
and
•
1024 bytes of dedicated endpoint FIFO
memory
•
8 – 512 byte data packet size supported
•
Configurable FIFO size for IN and OUT
direction of endpoint
3.4
I
2
S Interface
•
Industry standard I
2
S interface
transfer of digital audio data
•
Full duplex
•
Mono and stereo support
•
Configurable sample rate and sample
size
•
Support for
µ-law
compression and
expansion
for
SWRS055D
Page 6 of 243
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