C2510Fx / CC2511Fx
IRCON2 (0xE8) – CPU Interrupt Flag 5
Bit
Name
Reset
R/W
Description
7:5
0
R/W
Not used
4
3
2
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Watchdog timer interrupt flag
WDTIF
0
1
Interrupt not pending
Interrupt pending
Port 1 interrupt flag.
P1IF
0
1
Interrupt not pending
Interrupt pending
USART1 TX interrupt flag / I2S TX interrupt flag
UTX1IF /
I2STXIF
0
1
Interrupt not pending
Interrupt pending
USART0 TX interrupt flag
UTX0IF
0
1
Interrupt not pending
Interrupt pending
Port2 interrupt flag / USB interrupt flag
P2IF /
USBIF
0
1
Interrupt not pending
Interrupt pending
11.5.3 Interrupt Priority
group, the corresponding bits in IP0 and IP1
must be set as shown in Table 41 on Page 67.
The interrupts are grouped into six interrupt
priority groups and the priority for each group
is set by the registers IP0 and IP1. The
interrupt priority groups with assigned interrupt
sources are shown in Table 42. Each group is
assigned one of four priority levels, and by
default all six interrupt priority groups are
assign the lowest priority. In order to assign a
higher priority to an interrupt, i.e. to its interrupt
While an interrupt service request is in
progress, it cannot be interrupted by a lower or
same level interrupt. In the case when
interrupt requests of the same priority level are
received simultaneously, the polling sequence
shown in Table 43 is used to resolve the
priority of each requests.
IP1 (0xB9) – Interrupt Priority 1
Bit
Name
Reset
R/W
Description
7:6
0
R/W
Not used
5
4
3
2
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt group 5, priority control bit 1, refer to Table 41
Interrupt group 4, priority control bit 1, refer to Table 41
Interrupt group 3, priority control bit 1, refer to Table 41
Interrupt group 2, priority control bit 1, refer to Table 41
Interrupt group 1, priority control bit 1, refer to Table 41
Interrupt group 0, priority control bit 1, refer to Table 41
IP1_IPG5
IP1_IPG4
IP1_IPG3
IP1_IPG2
IP1_IPG1
IP1_IPG0
SWRS055D
Page 66 of 243
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
