C2510Fx / CC2511Fx
actually entered PM{1-3}, it is necessary to
clear the MODE bits before returning from all
ISRs associated with interrupts that can be
used to wake the device from PM{1-3}. It
should be noted that all port interrupts and
Sleep Timer interrupt are blocked when
SLEEP.MODEis different from 00, thus the time
interrupts are enabled during power modes. All
interrupts not to be used to wake up from PM
modes must be disabled before setting
SLEEP.MODE≠ 0.
13.1.4 Power Management Registers
This section describes the Power Management
registers. All register bits retain their previous
values when entering PM2 or PM3 unless
otherwise stated.
between setting SLEEP.MODE
≠
0
and
asserting PCON.IDLE should be as short as
possible. The SLEEP.MODE will be cleared to
00 by HW when power mode is entered, thus
PCON (0x87) – Power Mode Control
Bit
7:2
1
Name
Reset
R/W
Description
0
0
0
R/W
Not used
R0/W1 Reserved. Must be set to 0. Failure to do so will stop CPU from operating.
0
IDLE
R0/W1
H0
Power mode control. Writing a 1 to this bit forces CC2510Fx/CC2511Fx to enter
the power mode set by SLEEP.MODE. This bit is always read as 0.
All interrupt requests will clear this bit and CC2510Fx/CC2511Fx will reenter active
mode.
Note: See Section 13.1.3 for details on how this bit should be used.
SWRS055D
Page 76 of 243
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