C2510Fx / CC2511Fx
13.6 16-bit Timer, Timer 1
Timer 1 is an independent 16-bit timer which
supports typical timer/counter functions such
as input capture, output compare, and PWM
functions. The timer has three independent
capture/compare channels and uses one I/O
pin per channel.
The features of Timer 1 are as follows:
•
Three capture/compare channels
•
Rising, falling, or any edge input capture
•
Set, clear, or toggle output compare
•
Free-running, modulo
counter operation
or
up/down
CC2511Fx
. When the high speed RC oscillator is
used as system clock source, the highest
clock frequency used by Timer 1 is
f
XOSC
/2 for
CC2510Fx
and 12 MHz for
CC2511Fx
, given that
the HS RCOSC has been calibrated.
The counter operates as either a free-running
counter, a modulo counter, or as an up/down
counter for use in centre-aligned PWM. It can
also be used in DSM mode.
It is possible to read the 16-bit counter value
through the two 8-bit SFRs;
and
containing the high-order byte and
low-order byte respectively. When the
register is read, the high-order byte of the
counter at that instant is buffered in
T1CNTH
so that the high-order byte can be read from
T1CNTH
. Thus
shall always be read
first before reading
All write accesses to the
register will
reset the 16-bit counter.
The counter may produce an interrupt request
when the terminal count value (overflow) is
reached (see Section 13.6.2.1 - 13.6.2.3). It is
possible to start and halt the counter with
control register settings. The counter is
started when a value other than 00 is written to
If 00 is written to
the counter halts at its present value.
13.6.2
Timer 1 Operation
•
Clock prescaler for divide by 1, 8, 32, or
128
•
Interrupt
request
generation
on
capture/compare and when reaching the
terminal count value
•
Capture triggered by radio
•
DMA trigger function
•
Delta-Sigma Modulator (DSM) mode
Note: In the following sections, an
n
in the
register name represent the channel
number 0, 1, or 2 if nothing else is stated
13.6.1
16-bit Timer Counter
The timer consists of a 16-bit counter that
increments or decrements at each active clock
edge. The frequency of the active clock edges
is
given
by
and
is used to set
the timer tick speed. The timer tick speed will
vary from 203.125 kHz to 26 MHz for
CC2510Fx
and 187.5 kHz to 24 MHz for
CC2511Fx
(given
the use of a 26 MHz or 48 MHz crystal
respectively). Note that the clock speed of the
system clock is not affected by the
setting. The timer tick speed is further divided
in Timer 1 by the prescaler value set by
This prescaler value can be 1, 8,
32, or 128. Thus the lowest clock frequency
used by Timer 1 is 1.587 kHz and the highest
is 26 MHz when a 26 MHz crystal oscillator is
used as system clock source (
CC2510Fx
). The
lowest clock frequency used by Timer 1 is
1.465 kHz and the highest is 24 MHz for
In general, the control register
is used
to control the timer operation. The various
modes of operation are described in the
following three sections.
13.6.2.1 Free-running Mode
In free-running mode the counter starts from
0x0000 and increments at each active clock
edge. When the counter reaches the terminal
count value 0xFFFF (overflow), the counter is
loaded
with
0x0000
and
continues
incrementing its value as shown in Figure 28.
When 0xFFFF is reached, the
flag is set. The
flag is only
asserted if the corresponding interrupt mask
bit
is set. An interrupt request
is generated when both
and
are set to 1. The free-running
mode can be used to generate independent
time intervals and output signal frequencies.
SWRS055D
Page 111 of 243
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