C2510Fx / CC2511Fx
13.8 Sleep Timer
The Sleep Timer is used to control when the
CC2510Fx/CC2511Fx
exits from PM{0-2} and
hence the Sleep Timer can be used to
implement a wake up functionality which
enables
CC2510Fx/CC2511Fx
to periodically wake
up to active mode and listen for incoming RF
packets.
13.8.1
Sleep Timer Operation
t
Event
0
=
750
⋅
EVENT
0
⋅
2
5
⋅
WOR
_
RES
f
ref
If the 32.768 kHz crystal oscillator is used to
clock the Sleep Timer, t
Event0
is calculated as
follows:
t
Event
0
=
1
⋅
EVENT
0
⋅
2
5
⋅
WOR
_
RES
32768
This section describes the operation of the
timer.
Note: In this section of the document, f
Ref
is
used to denote the reference frequency for
the synthesizer.
For
CC2510Fx
f
ref
=
f
XOS
and for
The time from the
CC2510Fx/CC2511Fx
enters
PM2 until the next Event 0 is programmed to
appear (t
SLEEP
min
) should be larger than 11.08
ms when
f
ref
is 26 MHz and 12 ms when
f
ref
is
24 MHz (Sleep Timer clocked by the low
power RC oscillator).
CC2511Fx
,
f
ref
=
f
XOSC
2
When referring to the low power RCOSC,
calibrated values are assumed
The Sleep Timer consists of a 31-bit counter.
The appropriate bits of this counter are
selected according to a resolution setting
determined by the
register bits. The Sleep Timer is either clocked
by the 32.768 kHz crystal oscillator or by the
low power RC oscillator (f
ref
/ 750). The timer
can only be used in PM0, PM1, and PM2.
The Sleep Timer has a programmable timing
event called Event 0. While in PM0, PM1, or
PM2, reaching Event 0 will make the
CC2510Fx/CC2511Fx
enter active mode.
The time between two consecutive Event 0’s
(t
Event0
) is programmed with a mantissa value
given
by
WOREVT1.EVENT0
and
WOREVT0.EVENT0,
and an exponent value set
by
WORCTRL.WOR_RES.
When using the low
power RC oscillator to clock the Sleep Timer,
t
Event0
is given by:
t
SLEEP
min
=
750
⋅
384
f
ref
When the Sleep Timer is clocked by the
32.768 kHz crystal oscillator, t
SLEEP
min
= 11.72
ms (384/32768).
13.8.2
Sleep Timer and Power Mode 2
Entering PM2 has to be aligned to a positive
edge on the 32 kHz clock source. Note that
any updates to the compare value,
has to happen prior to this positive edge.
There has to be at least two positive edges on
the 32 kHz clock source between
being asserted and
entering PM2.
If
is changed to a value smaller than
the current counter value, an Event 0 will
occur immediately.
SWRS055D
Page 125 of 243
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