C2510Fx / CC2511Fx
14.18 Radio Registers
This Section describes all RF registers used for control and status for the radio.
0xDF2F: IOCFG2 – Radio Test Signal Configuration (P1_7)
Bit
7
6
5:0
GDO2_INV
GDO2_CFG[5:0]
Field Name
Reset
-
0
000000
R/W
R0
R/W
R/W
Description
Not used
Invert output, i.e. select active low (1) / high (0)
Debug output on P1_7 pin. See Table 73 for a
description of internal signals which can be output on
this pin for debug purpose
0xDF30: IOCFG1 – Radio Test Signal Configuration (P1_6)
Bit
7
Field Name
GDO_DS
Reset
0
R/W
R/W
Description
Enable / disable drive strength enhancement for all port
outputs. To be used below 2.6 V
0
1
6
GDO1_INV
0
R/W
Disable
Enable
Invert output
0
1
Active high
Active low
5:0
GDO1_CFG[5:0]
000000
R/W
Debug output on P1_6 pin. See Table 73 for a
description of internal signals which can be output on
this pin for debug purpose
0xDF31: IOCFG0 – Radio Test Signal Configuration (P1_5)
Bit
7
6
5:0
GDO0_INV
GDO0_CFG[5:0]
Field Name
Reset
-
0
000000
R/W
R0
R/W
R/W
Description
Not used
Invert output, i.e. select active low (1) / high (0)
Debug output on P1_5 pin. See Table 73 for a
description of internal signals which can be output on
this pin for debug purpose.
0xDF00: SYNC1 – Sync Word, High Byte
Bit
7:0
Field Name
SYNC[15:8]
Reset
0xD3
R/W
R/W
Description
8 MSB of 16-bit sync word
0xDF01: SYNC0 – Sync Word, Low Byte
Bit
7:0
Field Name
SYNC[7:0]
Reset
0x91
R/W
R/W
Description
8 LSB of 16-bit sync word
0xDF02: PKTLEN – Packet Length
Bit
7:0
Field Name
PACKET_LENGTH
Reset
0xFF
R/W
R/W
Description
Indicates the packet length when fixed length packets
are enabled. If variable length packets are used, this
value indicates the maximum length packets allowed
SWRS055D
Page 213 of 243
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