CD54HC670, CD74HC670, CD74HCT670
Functional Diagram
15
D0
D1
D2
D3
WE
RE
RA1
RA0
WA0
WA1
4
5
14
13
1
2
3
12
11
10
9
7
6
Q0
Q1
Q2
Q3
WRITE MODE SELECT TABLE
INPUTS
OPERATING
MODE
Write Data
WE
L
L
Data Latched
NOTE:
1. The Write Address (WA0 and WA1) to the “internal latches” must
be stable while WE is LOW for conventional operation.
H
D
N
L
H
X
INTERNAL
LATCHES
(NOTE 1)
L
H
No Change
Disabled
NOTE:
READ MODE SELECT TABLE
INPUTS
OPERATING
MODE
Read
INTERNAL
LATCHES
(NOTE 2)
L
H
X
OUTPUT
Q
N
L
H
(Z)
RE
L
L
H
2. The selection of the “internal latches” by Read Address (RA0 and
RA1) are not constrained by WE or RE operation.
H = High Voltage Level
L = Low Voltage Level
X= Don’t Care
Z = High Impedance “Off” State
2
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
