DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
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PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 40. Programmable PCLK Strobe Select
Power Up Requirements and PDB Pin
It is required to delay and release the PDB Signal after VDD (VDDn and VDDIO) power supplies have settled to
the recommended operating voltage. An external RC network can be connected to the PDB pin to ensure PDB
arrives after all the VDD has stabilized.
Built In Self Test
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and low-
speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for
system diagnostics.
BIST Configuration and Status
The chipset can be programmed into BIST mode using either pins or registers. By default BIST configuration is
controlled through pins. BIST can be configured via registers using BIST Control register (0x24). Pin based
configuration is defined as follows:
•
•
BISTEN : Enable the BIST Process
GPIO0 and GPIO1 : Defines the BIST clock source ( PCLK vs. various frequencies of internal OSC
Table 10. BIST Configuration
Deserializer GPIO[0:1]
Oscillator Source
External PCLK
Internal
BIST Frequency (MHz)
00
01
10
11
PCLK or External Oscillator
50
Internal
25
Internal
12.5
The BIST mode provides various options for source PCLK. Using external pins, GPIO0 and GPIO1 or using
registers, customer can program the BIST mode to use external PCLK or various OSC frequencies. The BIST
status can be monitored real time on PASS pin. For every frame with error(s), PASS pin toggles low for half
PCLK period. If two consecutive frames have errors, PCLK will toggle twice to allow counting of frames with
errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST run. The status can also
be read through I2C for the number of frames in errors. BIST status on PASS pin remains until it is changed by a
new BIST session or a reset. The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is
de-assserted. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK need to be
present.
The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is de-assserted. So for all
practical purposes, the BIST status can be monitored from register 0x25 i.e. BIST Error Count on the
DS90UB914 Deserializer. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK
need to be present.
Sample BIST Sequence
Step1. For the DS90UB913/914Q FPD-Link III chipset, BIST Mode is enabled via the BISTEN pin of
DS90UB914Q FPD-Link III deserializer. The desired clock source is selected through the GPIO0 and GPIO1 pins
as shown in Table 6.
50
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